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PIC16F526 Data Sheet
14-Pin, 8-Bit Flash Microcontroller
2010 Microchip Technology Inc.
DS41326D
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-044-7
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41326D-page 2
2010 Microchip Technology Inc.
PIC16F526
14-Pin, 8-Bit Flash Microcontroller
High-Performance RISC CPU:
* Only 33 Single-Word Instructions * All Single-Cycle Instructions except for Program Branches which are Two-Cycle * Two-Level Deep Hardware Stack * Direct, Indirect and Relative Addressing modes for Data and Instructions * Operating Speed: - DC - 20 MHz crystal oscillator - DC - 200 ns instruction cycle * On-chip Flash Program Memory: - 1024 x 12 * General Purpose Registers (SRAM): - 67 x 8 * Flash Data Memory: - 64 x 8
Low-Power Features/CMOS Technology:
* Standby current: - 100 nA @ 2.0V, typical * Operating current: - 11 A @ 32 kHz, 2.0V, typical - 175 A @ 4 MHz, 2.0V, typical * Watchdog Timer current: - 1 A @ 2.0V, typical - 7 A @ 5.0V, typical * High Endurance Program and Flash Data Memory cells: - 100,000 write Program Memory endurance - 1,000,000 write Flash Data Memory endurance - Program and Flash Data retention: >40 years * Fully Static Design * Wide Operating Voltage Range: 2.0V to 5.5V: - Wide temperature range - Industrial: -40C to +85C - Extended: -40C to +125C
Special Microcontroller Features:
* 8 MHz Precision Internal Oscillator: - Factory calibrated to 1% * In-Circuit Serial ProgrammingTM (ICSPTM) * In-Circuit Debugging (ICD) Support * Power-On Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with Dedicated On-Chip RC Oscillator for Reliable Operation * Programmable Code Protection * Multiplexed MCLR Input Pin * Internal Weak Pull-ups on I/O Pins * Power-Saving Sleep mode * Wake-Up from Sleep on Pin Change * Selectable Oscillator Options: - INTRC: 4 MHz or 8 MHz precision Internal RC oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - HS: High-speed crystal/resonator - LP: Power-saving, low-frequency crystal - EC: High-speed external clock input Program Memory Flash (words) PIC16F526 1024
Peripheral Features:
* 12 I/O Pins: - 11 I/O pins with individual direction control - 1 input-only pin - High current sink/source for direct LED drive - Wake-up on change - Weak pull-ups * 8-bit Real-time Clock/Counter (TMR0) with 8-bit Programmable Prescaler * Two Analog Comparators: - Comparator inputs and output accessible externally - One comparator with 0.6V fixed on-chip absolute voltage reference (VREF) - One comparator with programmable on-chip voltage reference (VREF) * Analog-to-Digital (A/D) Converter: - 8-bit resolution - 3-channel external programmable inputs - 1-channel internal input to internal absolute 0.6 voltage reference
Data Memory SRAM (bytes) 67 Flash (bytes) 64 I/O Comparators Timers 8-bit
Device
8-bit A/D Channels 3
12
2
1
2010 Microchip Technology Inc.
DS41326D-page 3
PIC16F526
FIGURE 1-1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM
VDD RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/VPP RC5/T0CKI RC4/C2OUT RC3
1
PIC16F526
2 3 4 5 6 7
14 13 12 11 10 9 8
VSS RB0/C1IN+/AN0/ICSPDAT RB1/C1IN-/AN1/ICSPCLK RB2/C1OUT/AN2 RC0/C2IN+ RC1/C2INRC2/CVREF
FIGURE 1-2:
16-PIN QFN DIAGRAM
VDD
PIC16F526
RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/VPP RC5/T0CKI
1
16 15 14 13 12 11 10 9 7 8
GND
NC
NC
RB0/C1IN+/AN0/ICSPDAT RB1/C1IN-/AN1/ICSPCLK RB2/C1OUT/AN2 RC0/C2IN+
2 3 4 5 6
RC4/C2OUT
RC2/CVREF
RC3
RC1/C2IN-
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PIC16F526
Table of Contents
1.0 General Description..................................................................................................................................................................... 7 2.0 PIC16F526 Device Varieties ...................................................................................................................................................... 9 3.0 Architectural Overview .............................................................................................................................................................. 11 4.0 Memory Organization ................................................................................................................................................................ 15 5.0 Flash Data Memory Control ...................................................................................................................................................... 23 6.0 I/O Port ...................................................................................................................................................................................... 27 7.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 37 8.0 Special Features of the CPU..................................................................................................................................................... 43 9.0 Analog-to-Digital (A/D) Converter.............................................................................................................................................. 59 10.0 Comparator(s) ........................................................................................................................................................................... 63 11.0 Comparator Voltage Reference Module.................................................................................................................................... 69 12.0 Instruction Set Summary ........................................................................................................................................................... 71 13.0 Development Support................................................................................................................................................................ 79 14.0 Electrical Characteristics ........................................................................................................................................................... 83 15.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 97 16.0 Packaging Information............................................................................................................................................................. 107 The Microchip Web Site .................................................................................................................................................................... 115 Customer Change Notification Service ............................................................................................................................................. 115 Customer Support ............................................................................................................................................................................. 115 Reader Response ............................................................................................................................................................................. 116 Index .................................................................................................................................................................................................. 117 Product Identification System................ ........................................................................................................................................... 119
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2010 Microchip Technology Inc.
DS41326D-page 5
PIC16F526
NOTES:
DS41326D-page 6
2010 Microchip Technology Inc.
PIC16F526
1.0 GENERAL DESCRIPTION
1.1 Applications
The PIC16F526 device from Microchip Technology is low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontrollers. It employs a RISC architecture with only 33 single-word/single-cycle instructions. All instructions are single cycle (200 s) except for program branches, which take two cycles. The PIC16F526 device delivers performance an order of magnitude higher than their competitors in the same price category. The 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easy to remember instruction set reduces development time significantly. The PIC16F526 product is equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from, including INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC16F526 device is available in the cost-effective Flash programmable version, which is suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC16F526 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a `C' compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM(R) PC and compatible machines. The PIC16F526 device fits in applications ranging from personal care appliances and security systems to lowpower remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16F526 device very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and PLDs in larger systems and coprocessor applications).
TABLE 1-1:
Clock Memory
FEATURES AND MEMORY OF PIC16F526
PIC16F526 Maximum Frequency of Operation (MHz) Flash Program Memory SRAM Data Memory (bytes) Flash Data Memory (bytes) 20 1024 67 64 TMR0 Yes 11 1 Yes Yes 33 14-pin PDIP, SOIC, TSSOP, QFN
Peripherals Features
Timer Module(s) Wake-up from Sleep on Pin Change I/O Pins Input Pins Internal Pull-ups In-Circuit Serial ProgrammingTM Number of Instructions Packages
The PIC16F526 device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC16F526 device uses serial programming with data pin RB0 and clock pin RB1.
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DS41326D-page 7
PIC16F526
NOTES:
DS41326D-page 8
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PIC16F526
2.0 PIC16F526 DEVICE VARIETIES
2.2
A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16F526 Product Identification System at the back of this data sheet to specify the correct part number.
Serialized Quick Turn ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.
2.1
Quick Turn Programming (QTP) Devices
Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
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DS41326D-page 9
PIC16F526
NOTES:
DS41326D-page 10
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PIC16F526
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16F526 device can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F526 device uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200 ns @ 20 MHz, 1 s @ 4 MHz) except for program branches. Table 3-1 below lists memory supported by the PIC16F526 device. The PIC16F526 device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-2, with the corresponding device pins described in Table 3-2.
TABLE 3-1:
PIC16F526 MEMORY
Program Memory Flash (words) 1024 Data Memory SRAM (bytes) 67 Flash (bytes) 64
Device
PIC16F526
The PIC16F526 device can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC16F526 device has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any Addressing mode. This symmetrical nature and lack of "special optimal situations" make programming with the PIC16F526 device simple, yet efficient. In addition, the learning curve is reduced significantly.
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DS41326D-page 11
PIC16F526
FIGURE 3-1: PIC16F526 BLOCK DIAGRAM
11
Flash Program Memory 1K x 12 Flash Data Memory 64x8
Program Bus 12 Instruction Reg
Program Counter
Data Bus
8
PORTB RB0/ICSPDAT RB1/ICSPCLK RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN PORTC
STACK1 STACK2
RAM 67 bytes File Registers RAM Addr (1) 9
Addr MUX Direct Addr 5 5-7 Indirect Addr
FSR Reg 8 3 STATUS Reg Comparator 1 MUX VREF ALU 8 W Reg Comparator 2
RC0 RC1 RC2 RC3 RC4 RC5/T0CKI C1IN+ C1INC1OUT
Device Reset Timer Instruction Decode and Control OSC1/CLKIN OSC2/CLKOUT Timing Generation Power-on Reset Watchdog Timer Internal RC Clock
C2IN+ C2INC2OUT
CVREF CVREF CVREF
Timer0 MCLR VDD, VSS 8-bit ADC AN0 AN1 AN2
VREF
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PIC16F526
TABLE 3-2:
Name RB0//C1IN+/AN0/ ICSPDAT
PIC16F526 PINOUT DESCRIPTION
Function RB0 C1IN+ AN0 ICSPDAT Input Type TTL AN AN ST TTL AN AN ST TTL -- AN TTL ST Output Type Description
CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. -- -- Comparator 1 input. ADC channel input.
CMOS ICSPTM mode Schmitt Trigger. CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. -- -- Comparator 1 input. ADC channel input.
RB1/C1IN-/AN1/ ICSPCLK
RB1 C1INAN1 ICSPCLK
CMOS ICSP mode Schmitt Trigger. CMOS Bidirectional I/O pin. CMOS Comparator 1 output. -- -- -- ADC channel input. Input pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. Weak pull-up always on if configured as MCLR. Programming voltage input.
RB2/C1OUT/AN2
RB2 C1OUT AN2
RB3/MCLR/VPP
RB3 MCLR
VPP RB4/OSC2/CLKOUT RB4 OSC2
HV TTL --
--
CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. XTAL Oscillator crystal output. Connections to crystal or resonator in Crystal Oscillator mode (XT, HS and LP modes only, PORTB in other modes).
CLKOUT RB5/OSC1/CLKIN RB5 OSC1 CLKIN RC0/C2IN+ RC1/C2INRC2/CVREF RC3 RC4/C2OUT RC5/T0CKI VDD VSS RC0 C2IN+ RC1 C2INRC2 CVREF RC3 RC4 C2OUT RC5 T0CKI VDD VSS
-- TTL XTAL ST TTL AN TTL AN TTL -- TTL TTL -- TTL ST -- --
CMOS EXTRC/INTRC CLKOUT pin (FOSC/4). CMOS Bidirectional I/O pin. -- -- -- -- AN Oscillator crystal input. External clock source input. Comparator 2 input. Comparator 2 input. Programmable Voltage Reference output.
CMOS Bidirectional I/O port. CMOS Bidirectional I/O port. CMOS Bidirectional I/O port. CMOS Bidirectional I/O port. CMOS Bidirectional I/O port. CMOS Comparator 2 output. CMOS Bidirectional I/O port. -- P P Timer0 Schmitt Trigger input pin. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, -- = Not used, TTL = TTL input, ST = Schmitt Trigger input, HV = High Voltage
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PIC16F526
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC PC Fetch INST (PC) Execute INST (PC - 1) PC + 1 PC + 2 Internal Phase Clock Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Fetch INST (PC + 1) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 1)
EXAMPLE 3-1:
1. MOVLW 03H 2. MOVWF PORTB 3. CALL SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
4. BSF PORTB, BIT1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed.
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PIC16F526
4.0 MEMORY ORGANIZATION
FIGURE 4-1: MEMORY MAP
000h
The PIC16F526 memories are organized into program memory and data memory (SRAM).The self-writable portion of the program memory called Flash data memory is located at addresses at 400h-43Fh. All Program mode commands that work on the normal Flash memory work on the Flash data memory. This includes bulk erase, row/column/cycling toggles, Load and Read data commands (Refer to Section 5.0 "Flash Data Memory Control" for more details). For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC16F526, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).
User Memory Space
On-chip User Program Memory (Page 0) On-chip User Program Memory (Page 1) Reset Vector
1FFh 200h 3FEh 3FFh 400h
Data Memory Space
Flash Data Memory User ID Locations Backup OSCCAL Locations 43Fh 440h 443h 444h 447h 448h
4.1
Program Memory Organization for the PIC16F526
Configuration Memory Space
Reserved 49Fh 4A0h Unimplemented 7FEh Configuration Word 7FFh
The PIC16F526 device has an 11-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Program memory is partitioned into user memory, data memory and configuration memory spaces. The user memory space is the on-chip user program memory. As shown in Figure 4-1, it extends from 0x000 to 0x3FF and partitions into pages, including Reset vector at address 0x3FF. The data memory space is the Flash data memory block and is located at addresses PC = 400h-43Fh. All Program mode commands that work on the normal Flash memory work on the Flash data memory block. This includes bulk erase, Load and Read data commands. The configuration memory space extends from 0x440 to 0x7FF. Locations from 0x448 through 0x49F are reserved. The user ID locations extend from 0x440 through 0x443. The Backup OSCCAL locations extend from 0x444 through 0x447. The Configuration Word is physically located at 0x7FF. Refer to "PIC16F526 Memory Programming Specification" (DS41317) for more details.
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PIC16F526
4.2 Data Memory (SRAM and FSRs)
4.2.1
Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The Special Function Registers are registers used by the CPU and peripheral functions for controlling desired operations of the PIC16F526. See Figure 4-1 for details. The PIC16F526 register file is composed of 16 Special Function Registers and 67 General Purpose Registers.
GENERAL PURPOSE REGISTER FILE
The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section 4.8 "Indirect Data Addressing: INDF and FSR Registers".
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
FIGURE 4-2:
REGISTER FILE MAP
00 20h INDF(1) TMR0 PCL STATUS FSR OSCCAL PORTB PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON General Purpose Registers INDF(1) EECON PCL STATUS FSR EEDATA EEADR PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON 01 40h INDF(1) TMR0 PCL STATUS FSR OSCCAL PORTB PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON Addresses map back to addresses in Bank 0. 4Fh 6Fh 50h General Purpose Registers 3Fh Bank 0 Bank 1 5Fh Bank 2 General Purpose Registers 7Fh Bank 3 70h General Purpose Registers 10 60h INDF(1) EECON PCL STATUS FSR EEDATA EEADR PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON 11
FSR<6:5> File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Fh 10h
2Fh 30h
General Purpose Registers 1Fh
Note 1:
Not a physical register. See Section 4.8 "Indirect Data Addressing: INDF and FSR Registers".
DS41326D-page 16
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PIC16F526
TABLE 4-1:
Addr N/A N/A 00h 01h/41h 02h(1) 03h 04h 05h/45h 06h/46h 07h 08h 09h 0Ah 0Bh 0Ch 21h/61h 25h/65h 26h/66h Legend: Note 1: Name TRIS OPTION INDF TMR0 PCL STATUS FSR OSCCAL PORTB PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON EECON EEDATA EEADR
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Bit 7 -- Bit 6 -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset --11 1111 1111 1111 xxxx xxxx xxxx xxxx 1111 1111 PA0 CAL4 RB5 RC5 C1POL ADCS1 TO CAL3 RB4 RC4 C1T0CS ADCS0 PD CAL2 RB3 RC3 C1ON CHS1 Z CAL1 RB2 RC2 C1NREF CHS0 DC CAL0 RB1 RC1 C1PREF GO/DONE C -- RB0 RC0 C1WU ADON 0001 1xxx 100x xxxx 1111 111--xx xxxx --xx xxxx q111 1111 1111 1100 xxxx xxxx C2POL VRR -- C2PREF2 -- FREE C2ON VR3 WRERR C2NREF VR2 WREN C2PREF1 VR1 WR C2WU VR0 RD q111 1111 001- 1111 ---0 x000 xxxx xxxx --xx xxxx Page # 27 19 22 37 21 18 22 20 27 28 63 61 62 64 69 23 23 23
I/O Control Register (PORTB, PORTC)
Contains control bits to configure Timer0 and Timer0/WDT prescaler Uses contents of FSR to Address Data Memory (not a physical register) Timer0 Module Register Low order 8 bits of PC RBWUF CAL6 -- -- C1OUT ANS1 CWUF CAL5 -- -- C1OUTEN ANS0
Indirect Data Memory Address Pointer
ADC Conversion Result C2OUT VREN -- -- C2OUTEN VROE -- --
SELF READ/WRITE DATA SELF READ/WRITE ADDRESS
x = unknown, u = unchanged, - = unimplemented, read as '0' (if applicable), q = value depends on condition. Shaded cells = unimplemented or unused The upper byte of the Program Counter is not directly accessible. See Section 4.6 "Program Counter" for an explanation of how to access these bits.
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PIC16F526
4.3 STATUS Register
This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 12.0 "Instruction Set Summary".
REGISTER 4-1:
R/W-0 RBWUF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STATUS: STATUS REGISTER
R/W-0 CWUF R/W-0 PA0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RBWUF: Wake-up from Sleep on Pin Change bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset CWUF: Wake-up from Sleep on Comparator Change bit 1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset PA0: Program Page Preselect bit 1 = Page 1 (000h-1FFh) 0 = Page 0 (200h-3FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F526
4.4 OPTION Register
Note: If TRIS bit is set to `0', the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of RBPU and RBWU). The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION <7:0> bits.
REGISTER 4-2:
W-1 RBWU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION: OPTION REGISTER
W-1 RBPU W-1 T0CS(1) W-1 T0SE W-1 PSA W-1 PS2 W-1 PS1 W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled T0CS: Timer0 Clock Source Select bit(1) 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
If the T0CS bit is set to `1', it will override the TRIS function on the T0CKI pin.
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4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to calibrate the 8 MHz internal oscillator macro. It contains 7 bits of calibration that uses a two's complement scheme for controlling the oscillator speed. See Register 4-3 for details.
REGISTER 4-3:
R/W-1 CAL6 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1
OSCCAL: OSCILLATOR CALIBRATION REGISTER
R/W-1 CAL5 R/W-1 CAL4 R/W-1 CAL3 R/W-1 CAL2 R/W-1 CAL1 R/W-1 CAL0 U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CAL<6:0>: Oscillator Calibration bits 0111111 = Maximum frequency * * * 0000001 0000000 = Center frequency 1111111 * * * 1000000 = Minimum frequency Unimplemented: Read as `0'
bit 0
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PIC16F526
4.6 Program Counter
4.6.1 EFFECTS OF RESET
As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The Program Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4-3). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-3). Instructions where the PCL is the destination, or modify PCL instructions, include MOVWF PCL, ADDWF PCL and BSF PCL,5. Note: Because bit 8 of the PC is cleared in the CALL instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code. The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is pre-selected. Therefore, upon a Reset, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.
4.7
Stack
The PIC16F526 device has a 2-deep, 12-bit wide hardware PUSH/POP stack. A CALL instruction will PUSH the current value of Stack 1 into Stack 2 and then PUSH the current PC value, incremented by one, into Stack Level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored. A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into Stack Level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in Stack Level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Note 1: There are no Status bits to indicate Stack Overflows or Stack Underflow conditions. 2: There are no instruction mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions.
FIGURE 4-3:
LOADING OF PC BRANCH INSTRUCTIONS
0 PCL
GOTO Instruction 10 9 8 7 PC
Instruction Word 7 PA0 0
Status CALL or Modify PCL Instruction 10 9 8 7 PC PCL Instruction Word Reset to `0' PA0 0 Status 0
7
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4.8 Indirect Data Addressing: INDF and FSR Registers
A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-1.
The INDF Register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR Register (FSR is a pointer). This is indirect addressing. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF Register indirectly results in a no-operation (although Status bits may be affected). The FSR is an 8-bit wide register. It is used in conjunction with the INDF Register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3). FSR<7> is unimplemented and read as `1'.
EXAMPLE 4-1:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF ;register ;inc pointer ;all done? ;NO, clear next ;YES, continue
NEXT
MOVLW MOVWF CLRF
INCF BTFSC GOTO CONTINUE : :
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Indirect Addressing (FSR) 0 6 5 4 3 2 1 0
(FSR) 6 5
Direct Addressing (opcode) 4 3 2 1
bank select
location select 00 00h 01 10 11
bank select
location select
Data Memory(1)
0Ch 0Dh Addresses map back to addresses in Bank 0. 0Fh 10h 2Fh 4Fh 6Fh
1Fh Bank 0
3Fh Bank 1
5Fh Bank 2
7Fh Bank 3
Note 1: For register map detail see Figure 4-1.
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5.0 FLASH DATA MEMORY CONTROL
3. 4. Perform a row erase of the row of interest. Write the new byte of data and any saved bytes back to the appropriate addresses in Flash data memory.
The Flash data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFRs).
5.1
Reading Flash Data Memory
To prevent accidental corruption of the Flash data memory, an unlock sequence is required to initiate a write or erase cycle. This sequence requires that the bit set instructions used to configure the EECON register happen exactly as shown in Example 2 and Example 3, depending on the operation requested.
To read a Flash data memory location the user must: * Write the EEADR register * Set the RD bit of the EECON register The value written to the EEADR register determines which Flash data memory location is read. Setting the RD bit of the EECON register initiates the read. Data from the Flash data memory read is available in the EEDATA register immediately. The EEDATA register will hold this value until another read is initiated or it is modified by a write operation. Program execution is suspended while the read cycle is in progress. Execution will continue with the instruction following the one that sets the WR bit. See Example 1 for sample code.
5.2.1
ERASING FLASH DATA MEMORY
A row must be manually erased before writing new data. The following sequence must be performed for a single row erase. 1. 2. 3. 4. Load EEADR with an address in the row to be erased. Set the FREE bit to enable the erase. Set the WREN bit to enable write access to the array. Set the WR bit to initiate the erase cycle.
If the WREN bit is not set in the instruction cycle after the FREE bit is set, the FREE bit will be cleared in hardware. If the WR bit is not set in the instruction cycle after the WREN bit is set, the WREN bit will be cleared in hardware. Sample code that follows this procedure is included in Example 2. Program execution is suspended while the erase cycle is in progress. Execution will continue with the instruction following the one that sets the WR bit.
EXAMPLE 1:
BANKSEL EEADR
READING FROM FLASH DATA MEMORY
; ; ;Data Memory ;Address to read ; ;EE Read ;W = EEDATA
MOVF DATA_EE_ADDR, W MOVWF EEADR BANKSEL EECON1 BSF EECON, RD MOVF EEDATA, W
EXAMPLE 2:
BANKSEL EEADR
ERASING A FLASH DATA MEMORY ROW
; LOAD ADDRESS OF ROW TO ; ERASE ; ; SELECT ERASE ; ENABLE WRITES ; INITITATE ERASE
Note: Only a BSF command will work to enable the Flash data memory read documented in Example 1. No other sequence of commands will work, no exceptions.
MOVLW MOVWF BSF BSF BSF
EE_ADR_ERASE EEADR EECON,FREE EECON,WREN EECON,WR
5.2
Writing and Erasing Flash Data Memory
Flash data memory is erased one row at a time and written one byte at a time. The 64-byte array is made up of eight rows. A row contains eight sequential bytes. Row boundaries exist every eight bytes. Generally, the procedure to write a byte of data to Flash data memory is: 1. 2. Identify the row containing the address where the byte will be written. If there is other information in that row that must be saved, copy those bytes from Flash data memory to RAM.
Note 1: The FREE bit may be set by any command normally used by the core. However, the WREN and WR bits can only be set using a series of BSF commands, as documented in Example 1. No other sequence of commands will work, no exceptions. 2: Bits <5:3> of the EEADR register indicate which row is to be erased.
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5.2.2 WRITING TO FLASH DATA MEMORY
Once a cell is erased, new data can be written. Program execution is suspended during the write cycle. The following sequence must be performed for a single byte write. 1. 2. 3. 4. Load EEADR with the address. Load EEDATA with the data to write. Set the WREN bit to enable write access to the array. Set the WR bit to initiate the erase cycle. Note 1: Only a series of BSF commands will work to enable the memory write sequence documented in Example 2. No other sequence of commands will work, no exceptions. 2: For reads, erases and writes to the Flash data memory, there is no need to insert a NOP into the user code as is done on midrange devices. The instruction immediately following the "BSF EECON,WR/RD" will be fetched and executed properly.
If the WR bit is not set in the instruction cycle after the WREN bit is set, the WREN bit will be cleared in hardware. Sample code that follows this procedure is included in Example 3.
5.3
Write Verify
EXAMPLE 3:
BANKSEL MOVLW MOVWF MOVLW MOVWF BSF BSF
WRITING A FLASH DATA MEMORY ROW
; ; ; ; ; ; LOAD ADDRESS
Depending on the application, good programming practice may dictate that data written to the Flash data memory be verified. Example 4 is an example of a write verify.
EEADR EE_ADR_WRITE EEADR EE_DATA_TO_WRITE EEDATA EECON,WREN EECON,WR
EXAMPLE 4:
MOVF
WRITE VERIFY OF FLASH DATA MEMORY
;EEDATA has not changed ;from previous write ;Read the value written ; ;Is data the same ;No, handle error ;Yes, continue
EEDATA, W EECON, RD EEDATA, W STATUS, Z WRITE_ERR
LOAD DATA INTO EEDATA REGISTER ENABLE WRITES INITITATE ERASE
BSF XORWF BTFSS GOTO
REGISTER 5-1:
R/W-x EEDATA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
EEDATA: FLASH DATA REGISTER
R/W-x EEDATA6 R/W-x EEDATA5 R/W-x EEDATA4 R/W-x EEDATA3 R/W-x EEDATA2 R/W-x EEDATA1 R/W-x EEDATA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEDATA<7:0>: 8-bits of data to be read from/written to data Flash
REGISTER 5-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
EEADR: FLASH ADDRESS REGISTER
U-0 -- R/W-x EEADR5 R/W-x EEADR4 R/W-x EEADR3 R/W-x EEADR2 R/W-x EEADR1 R/W-x EEADR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0'. EEADR<5:0>: 6-bits of data to be read from/written to data Flash
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PIC16F526
REGISTER 5-3:
U-0 -- bit 7 Legend: S = Bit can only be set R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EECON: FLASH CONTROL REGISTER
U-0 -- U-0 -- R/W-0 FREE R/W-0 WRERR R/W-0 WREN R/W-0 WR
R/W-0 RD bit 0
Unimplemented: Read as `0'. FREE: Flash Data Memory Row Erase Enable Bit 1 = Program memory row being pointed to by EEADR will be erased on the next write cycle. No write will be performed. This bit is cleared at the completion of the erase operation. 0 = Perform write only WRERR: Write Error Flag bit 1 = A write operation terminated prematurely (by device Reset) 0 = Write operation completed successfully WREN: Write Enable bit 1 = Allows write cycle to Flash data memory 0 = Inhibits write cycle to Flash data memory WR: Write Control bit 1 = Initiate a erase or write cycle 0 = Write/Erase cycle is complete RD: Read Control bit 1 = Initiate a read of Flash data memory 0 = Do not read Flash data memory
bit 3
bit 2
bit 1
bit 0
5.4
Code Protection
Code protection does not prevent the CPU from performing read or write operations on the Flash data memory. Refer to the code protection chapter for more information.
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NOTES:
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6.0 I/O PORT
6.2 PORTC
As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin's Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at highimpedance) since the I/O control registers are all set. PORTC is a 6-bit I/O register. Only the low-order 6 bits are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as `0's.
6.3
TRIS Register
6.1
PORTB
PORTB is a 6-bit I/O register. Only the low-order 6 bits are used (RB<5:0>). Bits 7 and 6 are unimplemented and read as `0's. Please note that RB3 is an input-only pin. The Configuration Word can set several I/O's to alternate functions. When acting as alternate functions, the pins will read as `0' during a port read. Pins RB0, RB1, RB3 and RB4 can be configured with weak pullups and also for wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If RB3/MCLR is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled.
The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f instruction. A `1' from a TRIS register bit puts the corresponding output driver in a High-Impedance mode. A `0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are RB3, which is input-only and the T0CKI pin, which may be controlled by the OPTION register. See Register 4-2. TRIS registers are "write-only". Active bits in these registers are set (output drivers disabled) upon Reset.
TABLE 6-1:
Device
WEAK PULL-UP ENABLED PINS
RB0 Weak Pull-up Yes RB1 Weak Pull-up RB3 Weak Pull-up(1) Yes Yes RB4 Weak Pull-up Yes
PIC16F526
Note 1: When MCLREN = 1, the weak pull-up on RB3/MCLR is always enabled.
REGISTER 6-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
PORTB: PORTB REGISTER
U-0 -- R/W-x RB5 R/W-x RB4 R/W-x RB3 R/W-x RB2 R/W-x RB1 R/W-x RB0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RB<5:0>: PORTB I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is 2010 Microchip Technology Inc.
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PIC16F526
REGISTER 6-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PORTC: PORTC REGISTER
U-0 -- R/W-x RC5 R/W-x RC4 R/W-x RC3 R/W-x RC2 R/W-x RC1 R/W-x RC0 bit 0
Unimplemented: Read as `0' RC<5:0>: PORTC I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is DS41326D-page 28
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PIC16F526
6.4 I/O Interfacing
FIGURE 6-1:
The equivalent circuit for an I/O port pin is shown in Figure 6-1. All port pins, except RB3 which is inputonly, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except RB3) can be programmed individually as input or output.
BLOCK DIAGRAM OF RB0 AND RB1 (with Weak Pullup and Wake-up on Change)
GPPU RBPU
Data Bus WR Port
D Data Latch CK
Q I/O Pin(1) Q
W Reg
D TRIS Latch CK
Q
TRIS `f'
Q
Reset ADC pin Ebl COMP pin Ebl
RD Port Q D
CK
Pin Change
ADC COMP Note 1: I/O pins have protection diodes to VDD and VSS.
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FIGURE 6-2: BLOCK DIAGRAM OF RB2
C1OUT Data Bus WR Port 0 I/O Pin(1) GPPU RBPU MCLRE Q
FIGURE 6-3:
BLOCK DIAGRAM OF RB3 (with Weak Pull-up and Wake-up on Change)
D Data Latch CK
Q
1
C1OUTEN W Reg D TRIS Latch CK Q Q Reset Input Pin
TRIS `f'
Reset ADC Pin Enable Data Bus RD Port Q D
CK RD Port Pin Change ADC Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: RB3/MCLR pin has a protection diode to VSS only.
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PIC16F526
FIGURE 6-4: BLOCK DIAGRAM OF RB4 (with Weak Pull-up and Wake-up on Change)
RBPU
FIGURE 6-5:
Data Bus WR Port
BLOCK DIAGRAM OF RB5
D Data Latch CK
Q I/O pin(1)
Q
Data Bus WR Port
D Data Latch CK
Q
0
W Reg
D TRIS Latch CK
Q
Q
1
I/O pin(1)
TRIS `f'
Q
W Reg
FOSC/4 D TRIS Latch CK Q Q
Reset (Note 2)
TRIS `f'
RD Port Reset INTOSC/RC/EC CLKOUT Enable (Note 2) Note 1: OSC2 Oscillator Circuit
I/O pins have protection diodes to VDD and VSS. oscillator.
2: Input mode is disabled when pin is used for
RD Port OSC1 Oscillator Circuit
Q
D
CK Pin Change
Note 1: 2:
I/O pins have protection diodes to VDD and VSS. Input mode is disabled when pin is used for oscillator.
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FIGURE 6-6: BLOCK DIAGRAM OF RC0/RC1 FIGURE 6-7: BLOCK DIAGRAM OF RC2
VROE
Data Bus WR Port
D Data Latch CK
Q I/O pin(1)
CVREF Data Bus WR Port
1 I/O PIN(1)
Q
D Data Latch CK
Q
0
W Reg
D TRIS Latch CK
Q
Q
TRIS `f'
Q
W Reg
D TRIS Latch CK
Q
Reset Comp Pin Enable
TRIS `f'
Q
Reset
RD Port COMP2 RD Port Note 1: I/O pins have protection diodes to VDD and VSS.
Note 1:
I/O pins have protection diodes to VDD and VSS.
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PIC16F526
FIGURE 6-8:
Data Bus WR Port
BLOCK DIAGRAM OF RC3
I/O Pin(1)
FIGURE 6-9:
BLOCK DIAGRAM OF RC4
C2OUT 0 I/O Pin(1)
D Data Latch CK
Q
Data Bus WR Port
D Data Latch CK
Q
1
Q
Q C2OUTEN
W Reg
D TRIS Latch CK
Q
W Reg
D TRIS Latch CK
Q
TRIS `f'
Q TRIS `f'
Q
Reset Reset
RD Port RD Port Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: I/O pins have protection diodes to VDD and VSS.
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FIGURE 6-10: BLOCK DIAGRAM OF RC5
Data Bus WR Port
I/O Pin(1) D Data Latch CK Q Q
W Reg
D TRIS Latch CK
Q
TRIS `f'
Q
T0CS
Reset
RD Port T0CKI Note 1: I/O pins have protection diodes to VDD and VSS.
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PIC16F526
TABLE 6-2:
Addr N/A N/A 03h 06h 07h
SUMMARY OF PORT REGISTERS
Bit 7 -- RBWU -- -- Bit 6 -- RBPU -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset --11 1111 PS0 C RB0 RC0 1111 1111 --xx xxxx --xx xxxx Value on All Other Resets --11 1111 1111 1111 --uu uuuu --uu uuuu
Name TRIS OPTION STATUS PORTB PORTC
I/O Control Register (PORTB, PORTC) TOCS PA0 RB5 RC5 TOSE TO RB4 RC4 PSA PD RB3 RC3 PS2 Z RB2 RC2 PS1 DC RB1 RC1
RBWUF CWUF
0001 1xxx qq0q quuu(1)
Legend: Shaded cells are not used by PORT registers, read as `0'. - = unimplemented, read as `0', x = unknown, u = unchanged, q = depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
TABLE 6-3:
Priority 1 2 3
I/O PINS ORDER OF PRECEDENCE
RB0 AN0 C1IN+ TRISB RB1 AN1 C1INTRISB RB2 AN2 C1OUT TRISB RB3 RB3/MCLR -- -- RC0 C2IN+ TRISC -- RC1 C2INTRISC -- RC2 CVREF TRISC -- RC4 C2OUT TRISC -- RC5 T0CKI TRISC --
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6.5
6.5.1
I/O Programming Considerations
BIDIRECTIONAL I/O PORTS
EXAMPLE 6-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT(e.g. DSTEMP)
Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and rewrite the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit 5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit 5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (say bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit 0 is switched into Output mode later on, the content of the data latch may now be unknown. Example 6-1 shows the effect of two sequential Read-Modify-Write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired OR", "wired AND"). The resulting high output currents may damage the chip.
;Initial PORTB Settings ;PORTB<5:3> Inputs ;PORTB<2:0> Outputs ; ; PORTB latch PORTB pins ; ------------------BCF PORTB, 5 ;--01 -ppp --11 pppp BCF PORTB, 4 ;--10 -ppp --11 pppp MOVLW 007h; TRIS PORTB ;--10 -ppp --11 pppp ; Note 1: The user may have expected the pin values to be `--00 pppp'. The 2nd BCF caused RB5 to be latched as the pin value (High).
6.5.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 6-11). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
FIGURE 6-11:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 PC + 3 NOP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetched RB<5:0> Port pin written here Instruction Executed MOVWF PORTB (Write to PORTB) Port pin sampled here MOVF PORTB,W (Read PORTB) PC MOVWF PORTB PC + 1 MOVF PORTB, W PC + 2 NOP
This example shows a write to PORTB followed by a read from PORTB. Data setup time = (0.25 TCY - TPD) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
NOP
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7.0 TIMER0 MODULE AND TMR0 REGISTER
There are two types of Counter mode. The first Counter mode uses the T0CKI pin to increment Timer0. It is selected by setting the T0CS bit of the OPTION register, setting the C1T0CS bit of the CM1CON0 register and setting the C1OUTEN bit of the CM1CON0 register. In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit of the OPTION register determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.1 "Using Timer0 with an External Clock". The second Counter mode uses the output of the comparator to increment Timer0. It can be entered in two different ways. The first way is selected by setting the T0CS bit of the OPTION register, and clearing the C1T0CS bit of the CM1CON0 register (C1OUTEN [CM1CON0<6>] does not affect this mode of operation). This enables an internal connection between the comparator and the Timer0. The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit, PSA of the OPTION register. Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 7.2 "Prescaler" details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 7-1.
The Timer0 module has the following features: * * * * 8-bit timer/counter register, TMR0 Readable and writable 8-bit software programmable prescaler Internal or external clock select: - Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit of the OPTION register. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register.
FIGURE 7-1:
TIMER0 BLOCK DIAGRAM
Data Bus
Comparator Output
FOSC/4 0
0 1 1 Programmable Prescaler(2) T0CS(1) 0
PSOUT Sync with Internal Clocks
8 TMR0 Reg
1 T0CKI pin T0SE(1)
PSOUT (2 cycle delay) Sync
PSA(1) 3 PS2(1), PS1(1), PS0(1)
C1T0CS(3) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer. 3: The C1T0CS bit is in the CM1CON0 register.
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FIGURE 7-2:
PC (Program Counter) Instruction Fetch Timer0 Instruction Executed T0
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC - 1 PC MOVWF TMR0 PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
T0 + 2
NT0
NT0 + 1
NT0 + 2
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
FIGURE 7-3:
PC (Program Counter) Instruction Fetch Timer0 Instruction Executed T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC - 1 PC MOVWF TMR0 PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
NT0
NT0 + 1
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
TABLE 7-1:
Addr 01h 08h 0Bh N/A N/A Name TMR0 CM1CON0 CM2CON0 OPTION TRIS(1)
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset xxxx xxxx C1ON C2ON PSA C1NREF C2NREF PS2 C1PREF C2PREF1 PS1 C1WU C2WU PS0 1111 1111 1111 1111 1111 1111 --11 1111 Value on All Other Resets uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 --11 1111
Timer0 - 8-bit Real-Time Clock/Counter C1OUT C2OUT RBWU -- C1OUTEN C2OUTEN RBPU -- C1POL C2POL T0CS C1T0CS C2PREF2 T0SE
I/O Control Register (PORTB, PORTC)
Legend: Note 1:
Shaded cells are not used by Timer0. - = unimplemented, x = unknown, u = unchanged. The TRIS of the T0CKI pin is overridden when T0CS = 1.
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7.1 Using Timer0 with an External Clock
When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4 TOSC (and a small RC delay of 4 Tt0H) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of Tt0H. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.
7.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-4). Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 2 Tt0H) and low for at least 2 TOSC (and a small RC delay of 2 Tt0H). Refer to the electrical specification of the desired device.
7.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-4 shows the delay from the external clock edge to the timer incrementing.
FIGURE 7-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler Output (2) External Clock/Prescaler Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (3) (1)
T0 + 2
Note 1: 2: 3:
Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = 4 TOSC max. External clock if no prescaler selected; prescaler output otherwise. The arrows indicate the points in time where sampling occurs.
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7.2 Prescaler
EXAMPLE 7-1:
An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 8.6 "Watchdog Timer (WDT)"). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice versa.
CHANGING PRESCALER (TIMER0 WDT)
CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 & Prescaler MOVLW b'00xx1111' CLRWDT ;PS<2:0> are 000 or 001 MOVLW b'00xx1xxx' ;Set Postscaler to OPTION ;desired WDT rate
The PSA and PS<2:0> bits of the OPTION register determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescaler contains all `0's.
To change the prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.
EXAMPLE 7-2:
CLRWDT MOVLW
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler b'xxxx0xxx' ;Select TMR0, new ;prescale value and ;clock source
7.2.1
SWITCHING PRESCALER ASSIGNMENT
OPTION
The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 71) must be executed when changing the prescaler assignment from Timer0 to the WDT.
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FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 Comparator Output 0 1 1 T0CKI Pin T0SE(1) C1TOCS 0 1 M U X T0CS(1) M U X 8 1 0 M U X Sync 2 Cycles TCY (= FOSC/4)
TMR0 Reg
PSA(1)
8-bit Prescaler 8 8-to-1 MUX PS<2:0>(1)
Watchdog Timer
PSA WDT Enable bit
(1)
0 MUX
1 PSA(1)
WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
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NOTES:
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8.0 SPECIAL FEATURES OF THE CPU
The PIC16F526 device has a Watchdog Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS, XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable. If using INTRC or EXTRC, there is a 1 ms delay only on VDD power-up. With this timer on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low current Power-Down mode. The user can wake-up from Sleep through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4/8 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC16F526 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection. These features are: * Oscillator Selection * Reset: - Power-on Reset (POR) - Device Reset Timer (DRT) - Wake-up from Sleep on Pin Change * Watchdog Timer (WDT) * Sleep * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM * Clock Out
8.1
Configuration Bits
The PIC16F526 Configuration Words consist of 12 bits. Configuration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type; one bit is the Watchdog Timer enable bit, one bit is the MCLR enable bit and one bit is for code protection (Register 8-1).
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REGISTER 8-1:
CPDF bit 7 bit 7 CPDF: Code Protection bit - Flash Data Memory 1 = Code protection off 0 = Code protection on IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC frequency 0 = 4 MHz INTOSC frequency MCLRE: Master Clear Enable bit 1 = RB3/MCLR pin functions as MCLR 0 = RB3/MCLR pin functions as RB3, MCLR internally tied to VDD CP: Code Protection bit - User Program Memory 1 = Code protection off 0 = Code protection on WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<2:0>: Oscillator Selection bits 000 = LP oscillator and 18 ms DRT 001 = XT oscillator and 18 ms DRT 010 = HS oscillator and 18 ms DRT 011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT(1) 100 = INTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT(1) 101 = INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT(1) 110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT(1) 111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT(1)
CONFIG: CONFIGURATION WORD REGISTER
IOSCFS MCLRE CP WDTE FOSC2 FOSC1 FOSC0 bit 0
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: Refer to the "PIC16F526 Memory Programming Specification", DS41317 to determine how to access the Configuration Word. 2: DRT length (18 ms or 1 ms) is a function of Clock mode selection. It is the responsibility of the application designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in acceptable operation. Refer to Section 14.1 "DC Characteristics: PIC16F526 (Industrial)" and Section 14.2 "DC Characteristics: PIC16F526 (Extended)" for VDD rise time and stability requirements for this mode of operation.
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8.2
8.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 8-1:
The PIC16F526 device can be operated in up to six different oscillator modes. The user can program up to three Configuration bits (FOSC<2:0>). To select one of these modes: * * * * * * LP: XT: HS: INTRC: EXTRC: EC: Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator Internal 4/8 MHz Oscillator External Resistor/Capacitor External High-Speed Clock Input
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16F526 Sleep RF(3) OSC2 To internal logic
C1(1)
XTAL RS(2)
C2(1) Note 1: 2: 3:
8.2.2
CRYSTAL OSCILLATOR/CERAMIC RESONATORS
In HS, XT or LP modes, a crystal or ceramic resonator is connected to the RB5/OSC1/CLKIN and RB4/OSC2/ CLKOUT pins to establish oscillation (Figure 8-1). The PIC16F526 oscillator designs require the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS, XT or LP modes, the device can have an external clock source drive the RB5/OSC1/CLKIN pin (Figure 8-2). In this mode, the output drive levels on the OSC2 pin are very weak. If the part is used in this fashion, then this pin should be left open and unloaded. Also when using this mode, the external clock should observe the frequency limits for the Clock mode chosen (HS, XT or LP). Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. 2: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required.
See Capacitor Selection tables for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF approx. value = 10 M.
FIGURE 8-2:
EXTERNAL CLOCK INPUT OPERATION (HS, XT, LP OR EC OSC CONFIGURATION)
EC, HS, XT, LP
Clock From ext. system OSC2/CLKOUT/RB4 RB5/OSC1/CLKIN PIC16F526 OSC2/CLKOUT/RB4(1)
Note 1:
RB4 is available in EC mode only.
TABLE 8-1:
Osc Type XT HS Note 1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS
Cap. Range C1 30 pF 10-47 pF Cap. Range C2 30 pF 10-47 pF
Resonator Freq. 4.0 MHz 16 MHz
These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
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TABLE 8-2:
Osc Type LP XT
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR(2)
Cap. Range C1 15 pF 47-68 pF 15 pF 15 pF 15-47 pF Cap. Range C2 15 pF 47-68 pF 15 pF 15 pF 15-47 pF
Resonator Freq. 32 kHz(1) 200 kHz 1 MHz 4 MHz 20 MHz
Figure 8-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 8-4:
HS Note 1: 2:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
330 74AS04 74AS04 CLKIN To Other Devices
For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
330 74AS04 0.1 mF XTAL
PIC16F526
8.2.3
EXTERNAL CRYSTAL OSCILLATOR CIRCUIT
8.2.4
EXTERNAL RC OSCILLATOR
Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 8-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.
For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 8-5 shows how the R/C combination is connected to the PIC16F526 device. For REXT values below 3.0 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 5.0 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Section 14.0 "Electrical Characteristics" shows RC frequency variation from part-to-part due to normal process variation. The variation is larger for larger values of R (since leakage current variation will affect RC frequency more for large R) and for smaller values of C (since variation of input capacitance will affect RC frequency more).
FIGURE 8-3:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices 4.7k 74AS04 74AS04 CLKIN PIC16F526 10k XTAL
+5V 10k
10k 20 pF 20 pF
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Also, see the Electrical Specifications section for variation of oscillator frequency due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for given R, C and VDD values.
8.2.5
INTERNAL 4/8 MHz RC OSCILLATOR
FIGURE 8-5:
VDD REXT
EXTERNAL RC OSCILLATOR MODE
The internal RC oscillator provides a fixed 4/8 MHz (nominal) system clock at VDD = 5V and 25C, (see Section 14.0 "Electrical Characteristics" for information on variation over voltage and temperature). In addition, a calibration instruction is programmed into the last address of memory, which contains the calibration value for the internal RC oscillator. This location is always non-code protected, regardless of the codeprotect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the Reset vector. This will load the W register with the calibration value upon Reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will "trim" the internal oscillator to remove process variation from the oscillator frequency. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later.
OSC1
Internal clock
CEXT VSS FOSC/4
N PIC16F526 OSC2/CLKOUT
For the PIC16F526 device, only bits 7:1 of OSCCAL are used for calibration. See Register 4-3 for more information. Note: The bit 0 of the OSCCAL register is unimplemented and should be written as `0' when modifying OSCCAL for compatibility with future devices.
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8.3 Reset
The device differentiates between various kinds of Reset: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Time-out Reset during normal operation WDT Time-out Reset during Sleep Wake-up from Sleep on pin change Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset. Most other registers are reset to "Reset state" on Power-on Reset (POR), MCLR, WDT or Wake-up on pin change Reset during normal operation. They are not affected by a WDT Reset during Sleep or MCLR Reset during Sleep, since these Resets are viewed as resumption of normal operation. The exceptions to this are TO, PD and RBWUF bits. They are set or cleared differently in different Reset situations. These bits are used in software to determine the nature of Reset. See Table 8-3 for a full description of Reset states of all registers.
TABLE 8-3:
Register W INDF TMR0 PCL STATUS FSR OSCCAL PORTB PORTC CMICON0 ADCON0 ADRES CM2CON0 VRCON OPTION TRISB TRISC EECON EEDATA EEADR
RESET CONDITIONS FOR REGISTERS
Address -- 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch -- -- -- 21h/61h 25h/65h 26h/66h Power-on Reset qqqq qqq0(1) xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 100x xxxx 1111 111--xx xxxx --xx xxxx q111 1111 1111 1100 xxxx xxxx q111 1111 001-1111 1111 1111 --11 1111 --11 1111 ---0 x000 xxxx xxxx --xx xxxx MCLR Reset, WDT Time-out, Wake-up On Pin Change qqqq qqq0(1) uuuu uuuu uuuu uuuu 1111 1111 qq0q quuu(2) 1uuu uuuu uuuu uuu--uu uuuu --uu uuuu quuu uuuu 1111 1100 uuuu uuuu quuu uuuu uuu-uuuu 1111 1111 --11 1111 --11 1111 ---0 q000 uuuu uuuu --uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table 8-4 for Reset value for specific conditions.
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TABLE 8-4:
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset during Sleep WDT Reset normal operation Wake-up from Sleep on pin change Wake-up from Sleep on comparator change Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0'.
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h 0001 1xxx 000u uuuu 0001 0uuu 0000 0uuu 0000 uuuu 1001 0uuu 0101 0uuu
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8.3.1 MCLR ENABLE
This Configuration bit, when unprogrammed (left in the `1' state), enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD and the pin is assigned to be a I/O. See Figure 8-6. The Power-on Reset circuit and the Device Reset Timer (see Section 8.5 "Device Reset Timer (DRT)") circuit are closely related. On power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms or 1 ms, it will reset the Reset latch and thus end the on-chip Reset signal. A power-up example where MCLR is held low is shown in Figure 8-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high.
RB3/MCLR/VPP MCLRE Internal MCLR
FIGURE 8-6:
RBWU
MCLR SELECT
8.4
Power-on Reset (POR)
The PIC16F526 device incorporates an on-chip Poweron Reset (POR) circuitry, which provides an internal chip Reset for most power-up situations. The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program the RB3/MCLR/VPP pin as MCLR and tie through a resistor to VDD, or program the pin as RB3. An internal weak pull-up resistor is implemented using a transistor (refer to Table 14-5 for the pull-up resistor ranges). This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Section 14.0 "Electrical Characteristics" for details. When the device starts normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating parameters are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 8-7.
In Figure 8-9, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be RB3. The VDD is stable before the start-up timer times out and there is no problem in getting a proper Reset. However, Figure 8-10 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip may not function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 8-9). Note: When the device starts normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.
For additional information, refer to Application Notes AN522 "Power-Up Considerations" (DS00522) and AN607 "Power-up Trouble Shooting" (DS00607).
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PIC16F526
FIGURE 8-7:
VDD Power-up Detect RB3/MCLR/VPP MCLR Reset S MCLRE WDT Time-out Pin Change Sleep Comparator Change Wake-up on Comparator Change WDT Reset R Start-up Timer (10 ms, 1.125 ms or 18 ms) Q CHIP Reset Q POR (Power-on Reset)
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Wake-up on pin Change Reset
FIGURE 8-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD MCLR Internal POR TDRT
DRT Time-out Internal Reset
FIGURE 8-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR Internal POR TDRT
DRT Time-out
Internal Reset
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FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1 VDD MCLR Internal POR TDRT
DRT Time-out
Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
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8.5 Device Reset Timer (DRT)
TABLE 8-5:
Oscillator Configuration HS, XT, LP EC INTOSC, EXTRC
TYPICAL DRT PERIODS
POR Reset 18 ms 1.125 ms 1.125 ms Subsequent Resets 18 ms 10 s 10 s
On the PIC16F526 device, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 8-5). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a Reset condition after MCLR has reached a logic high (VIH MCLR) level. Programming RB3/MCLR/VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases. This allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the RB3/ MCLR/VPP pin as a general purpose input. The Device Reset Time delays will vary from chip-tochip due to VDD, temperature and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out from Sleep. This is particularly important for applications using the WDT to wake from Sleep mode automatically. Reset sources are POR, MCLR, WDT time-out and wake-up on pin or comparator change. See Section 8.9.2 "Wake-up from Sleep", Notes 1, 2 and 3.
8.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst-case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device Reset. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT wake-up Reset.
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the external RC oscillator of the RB5/OSC1/CLKIN pin and the internal 4/8 MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset. The TO bit of the STATUS register will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration WDTE as a `0' (see Section 8.1 "Configuration Bits"). Refer to the PIC16F526 Programming Specifications to determine how to access the Configuration Word.
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FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source (Figure 7-1) 0 Watchdog Time 1
M U X
Postscaler
8-to-1 MUX WDT Enable Configuration Bit PSA
PS<2:0>(1)
To Timer0 (Figure 7-4) 0 MUX 1 PSA(1)
WDT Time-out
Note 1:
PSA, PS<2:0> are bits in the OPTION register.
TABLE 8-6:
Address N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name Bit 7 RBWU Bit 6 RBPU Bit 5 T0CS Bit 4 T0SE Bit 3 PSA Bit 2 PS2 Bit 1 PS1 Bit 0 PS0 Value on Power-On Reset 1111 1111 Value on All Other Resets 1111 1111
OPTION
Legend: Shaded boxes = Not used by Watchdog Timer.
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8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, RBWUF, CWUF)
FIGURE 8-12:
VDD VDD 33k 10k Q1 MCLR(2) PIC12F510 PIC16F506
BROWN-OUT PROTECTION CIRCUIT 1
The TO, PD and RBWUF bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset.
TABLE 8-7:
TO/PD/RBWUF/CWUF STATUS AFTER RESET
Reset Caused By WDT wake-up from Sleep WDT time-out (not from Sleep) MCLR wake-up from Sleep Power-up MCLR not during Sleep Wake-up from Sleep on pin change Wake up from Sleep on comparator change
R2 R1 Note 1: 2:
40k(1)
CWUF RBWUF TO PD 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 u 1 1 0 u 0 1 u 0 0
This circuit will activate Reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). Pin must be configured as MCLR.
FIGURE 8-13:
VDD
BROWN-OUT PROTECTION CIRCUIT 2
VDD PIC12F510 PIC16F506 MCLR(2)
Q1
Legend: u = unchanged Note 1: The TO, PD and RBWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR input does not change the TO, PD and RBWUF Status bits.
40k(1)
Note 1:
This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD * R1 R1 + R2 = 0.7V
8.8
Reset on Brown-out
2:
A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC16F526 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 8-12 and Figure 8-13.
Pin must be configured as MCLR.
FIGURE 8-14:
VDD MCP809 VSS RST
BROWN-OUT PROTECTION CIRCUIT 3
VDD
Bypass Capacitor VDD
MCLR PIC12F510 PIC16F506
Note:
This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. There are 7 different trip point selections to accommodate 5V to 3V systems.
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PIC16F526
8.9 Power-down Mode (Sleep)
8.9.2 WAKE-UP FROM SLEEP
A device may be powered down (Sleep) and later powered up (wake-up from Sleep). The device can wake-up from Sleep through one of the following events: 1. 2. 3. 4. An external Reset input on RB3/MCLR/VPP pin, when configured as MCLR. A Watchdog Timer Time-out Reset (if WDT was enabled). A change on input pin RB0, RB1, RB3 or RB4 when wake-up on change is enabled. A change in one of the comparator output bits, C1OUT or C2OUT (if comparator wake-up is enabled).
8.9.1
SLEEP
The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit of the STATUS register is set, the PD bit of the STATUS register is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or high-impedance). Note: A Reset generated by a WDT time-out does not drive the MCLR pin low.
For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the RB3/ MCLR/VPP pin must be at a logic high level if MCLR is enabled.
These events cause a device Reset. The TO, PD and CWUF/RBWUF bits can be used to determine the cause of device Reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The CWUF bit indicates a change in a comparator output state while the device was in Sleep. The RBWUF bit indicates a change in state while in Sleep at pins RB0, RB1, RB3 or RB4 (since the last file or bit operation on RB port). Note: Caution: Right before entering Sleep, read the input pins. When in Sleep, wake-up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode.
The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. Note: Caution: Right before entering Sleep, read the comparator Configuration register(s) CM1CON0 and CM2CON0. When in Sleep, wake-up occurs when the comparator output bit C1OUT and C2OUT change from the state they were in at the last reading. If a wake-up on comparator change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately, even if no pins change while in Sleep mode.
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PIC16F526
8.10 Program Verification/Code Protection
FIGURE 8-15: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC16F526 VDD VSS MCLR/VPP RB1 RB0 VDD To Normal Connections
If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the code protection bit setting. The last memory location can be read regardless of the code protection bit setting on the PIC16F526 device.
External Connector Signals +5V 0V VPP CLK Data
8.11
ID Locations
Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as `0's.
8.12
In-Circuit Serial ProgrammingTM
The PIC16F526 microcontroller can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware, to be programmed. The devices are placed into a Program/Verify mode by holding the RB1 and RB0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB1 becomes the programming clock and B0 becomes the programming data. Both RB1 and RB0 are Schmitt Trigger inputs in this mode. After Reset, a 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a Load or a Read. For complete details of serial programming, please refer to the PIC16F526 Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure 8-15.
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NOTES:
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9.0 ANALOG-TO-DIGITAL (A/D) CONVERTER
Note: It is the users responsibility to ensure that use of the ADC and comparator simultaneously on the same pin, does not adversely affect the signal being monitored or adversely effect device operation.
The A/D Converter allows conversion of an analog signal into an 8-bit digital signal.
9.1
Clock Divisors
The ADC has 4 clock source settings ADCS<1:0>. There are 3 divisor values 16, 8 and 4. The fourth setting is INTOSC with a divisor of 4. These settings will allow a proper conversion when using an external oscillator at speeds from 20 MHz to 350 kHz. Using an external oscillator at a frequency below 350 kHz requires the ADC oscillator setting to be INTOSC/4 (ADCS<1:0> = 11) for valid ADC results. The ADC requires 13 TAD periods to complete a conversion. The divisor values do not affect the number of TAD periods required to perform a conversion. The divisor values determine the length of the TAD period. When the ADCS<1:0> bits are changed while an ADC conversion is in process, the new ADC clock source will not be selected until the next conversion is started. This clock source selection will be lost when the device enters Sleep. Note: The ADC clock is derived from the instruction clock. The ADCS divisors are then applied to create the ADC clock
When the CHS<1:0> bits are changed during an ADC conversion, the new channel will not be selected until the current conversion is completed. This allows the current conversion to complete with valid results. All channel selection information will be lost when the device enters Sleep.
TABLE 9-1:
CHANNEL SELECT (ADCS) BITS AFTER AN EVENT
ADCS<1:0> 11 CS<1:0> CS<1:0> 11 11
Event MCLR Conversion completed Conversion terminated Power-on Wake from Sleep
9.1.4
THE GO/DONE BIT
9.1.1
VOLTAGE REFERENCE
There is no external voltage reference for the ADC. The ADC reference voltage will always be VDD.
9.1.2
ANALOG MODE SELECTION
The ANS<1:0> bits are used to configure pins for analog input. Upon any Reset, ANS<1:0> defaults to 11. This configures pins AN0, AN1 and AN2 as analog inputs. The comparator output, C1OUT, will override AN2 as an input if the comparator output is enabled. Pins configured as analog inputs are not available for digital output. Users should not change the ANS bits while a conversion is in process. ANS bits are active regardless of the condition of ADON.
The GO/DONE bit is used to determine the status of a conversion, to start a conversion and to manually halt a conversion in process. Setting the GO/DONE bit starts a conversion. When the conversion is complete, the ADC module clears the GO/DONE bit. A conversion can be terminated by manually clearing the GO/DONE bit while a conversion is in process. Manual termination of a conversion may result in a partially converted result in ADRES. The GO/DONE bit is cleared when the device enters Sleep, stopping the current conversion. The ADC does not have a dedicated oscillator, it runs off of the instruction clock. Therefore, no conversion can occur in sleep. The GO/DONE bit cannot be set when ADON is clear.
9.1.3
ADC CHANNEL SELECTION
The CHS bits are used to select the analog channel to be sampled by the ADC. The CHS<1:0> bits can be changed at any time without adversely effecting a conversion. To acquire an analog signal the CHS<1:0> selection must match one of the pin(s) selected by the ANS<1:0> bits. When the ADC is on (ADON = 1) and a channel is selected that is also being used by the comparator, then both the comparator and the ADC will see the analog voltage on the pin.
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9.1.5 SLEEP
This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and powerdown the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may contain a partial conversion. At least 1 bit must have been converted prior to Sleep to have partial conversion data in ADRES. The ADCS and CHS bits are reset to their default condition; ANS<1:0> = 11 and CHS<1:0> = 11. * For accurate conversions, TAD must meet the following: * 500 ns < TAD < 50 s * TAD = 1/(FOSC/divisor) Shaded areas indicate TAD out of range for accurate conversions. If analog input is desired at these frequencies, use INTOSC/8 for the ADC clock source.
TABLE 9-2:
Source INTOSC FOSC FOSC FOSC
TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
Divisor 4 4 8 16 20 MHz -- .2 s .4 s .8 s 16 MHz -- .25 s .5 s 1 s 8 MHz 4 MHz 1 MHz .5 s .5 s 1 s 2 s 1 s 1 s 2 s 4 s -- 4 s 8 s 16 s 500 kHz -- 8 s 16 s 32 s 350 kHz -- 11 s 23 s 46 s 200 kHz -- 20 s 40 s 80 s 100 kHz -- 40 s 80 s 160 s 32 kHz -- 125 s 250 s 500 s
ADCS <1:0> 11 10 01 00
TABLE 9-3:
Entering Sleep Wake or Reset
EFFECTS OF SLEEP ON ADCON0
ANS1 ANS0 ADCS1 1 1 ADCS0 1 1 CHS1 1 1 CHS0 1 1 GO/DONE 0 0 ADON 0 0 Unchanged Unchanged 1 1
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PIC16F526
9.1.6 ANALOG CONVERSION RESULT REGISTER
The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0). A `leading one' is then right shifted into the ADRES to serve as an internal conversion complete bit. As each bit weight, starting with the MSB, is converted, the leading one is shifted right and the converted bit is stuffed into ADRES. After a total of 9 right shifts of the `leading one' have taken place, the conversion is complete; the `leading one' has been shifted out and the GO/DONE bit is cleared. If the GO/DONE bit is cleared in software during a conversion, the conversion stops. The data in ADRES is the partial conversion result. This data is valid for the bit weights that have been converted. The position of the `leading one' determines the number of bits that have been converted. The bits that were not converted before the GO/DONE was cleared are unrecoverable.
REGISTER 9-1:
R/W-1 ANS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6
ADCON0: A/D CONTROL REGISTER
R/W-1 ANS0 R/W-1 ADCS1 R/W-1 ADCS0 R/W-1 CHS1 R/W-1 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ANS<1:0>: ADC Analog Input Pin Select bits(1), (2), (5) 00 = No pins configured for analog input 01 = AN2 configured as an analog input 10 = AN2 and AN0 configured as analog inputs 11 = AN2, AN1 and AN0 configured as analog inputs ADCS<1:0>: ADC Conversion Clock Select bits 00 = FOSC/16 01 = FOSC/8 10 = FOSC/4 11 = INTOSC/4 CHS<1:0>: ADC Channel Select bits(3, 5) 00 = Channel AN0 01 = Channel AN1 10 = Channel AN2 11 = 0.6V absolute voltage reference GO/DONE: ADC Conversion Status bit(4) 1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC is done converting. 0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process terminates the current conversion. ADON: ADC Enable bit 1 = ADC module is operating 0 = ADC module is shut-off and consumes no power When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin function previously defined. The only exception to this is the comparator, where the analog input to the comparator and the ADC will be active at the same time. It is the users responsibility to ensure that the ADC loading on the comparator input does not affect their application. The ANS<1:0> bits are active regardless of the condition of ADON. CHS<1:0> bits default to 11 after any Reset. If the ADON bit is clear, the GO/DONE bit cannot be set. C1OUT, when enabled, overrides AN2.
bit 5-4
bit 3-2
bit 1
bit 0
Note 1:
2: 3: 4: 5:
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REGISTER 9-2:
R/W-X ADRES7 bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES: A/D CONVERSION RESULTS REGISTER
R/W-X ADRES6 R/W-X ADRES5 R/W-X ADRES4 R/W-X ADRES3 R/W-X ADRES2 R/W-X ADRES1 R/W-X ADRES0 bit 0
EXAMPLE 9-1:
PERFORMING AN ANALOG-TO-DIGITAL CONVERSION
EXAMPLE 9-2:
CHANNEL SELECTION CHANGE DURING CONVERSION
;configure A/D
;Sample code operates out of BANK0
MOVLW 0xF1 ;configure A/D MOVWF ADCON0 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop0 MOVF ADRES, W ;read result MOVWF result0 ;save result ;setup for read of ;channel 1 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop1 MOVF ADRES, W ;read result MOVWF result1 ;save result BSF ADCON0, 3 ;setup for read of BCF ADCON0, 2 ;channel 2 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop2 MOVF ADRES, W ;read result MOVWF result2 ;save result BSF ADCON0, 2
loop0
loop0
;start conversion ;setup for read of ;channel 1 BTFSC ADCON0, 1;wait for `DONE' GOTO loop0 MOVF ADRES, W ;read result MOVWF result0 ;save result BSF ADCON0, 1 ;start conversion BSF ADCON0, 3 ;setup for read of BCF ADCON0, 2 ;channel 2 BTFSC ADCON0, 1;wait for `DONE' GOTO loop1 MOVF ADRES, W ;read result MOVWF result1 ;save result BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop2 MOVF ADRES, W ;read result MOVWF result2 ;save result CLRF ADCON0 ;optional: returns ;pins to Digital mode and turns off ;the ADC module
MOVLW 0xF1 MOVWF ADCON0 BSF ADCON0, 1 BSF ADCON0, 2
loop1
loop1
loop2
loop2
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PIC16F526
10.0 COMPARATOR(S)
and a This device contains two comparators comparator voltage reference.
REGISTER 10-1:
R-1 C1OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 7
CM1CON0: COMPARATOR C1 CONTROL REGISTER
R/W-1 R/W-1 C1POL R/W-1 C1T0CS R/W-1 C1ON R/W-1 C1NREF R/W-1 C1PREF R/W-1 C1WU bit 0
C1OUTEN
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
C1OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VINC1OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C1OUT pin 0 = Output of comparator is placed in the C1OUT pin C1POL: Comparator Output Polarity bit(2) 1 = Output of comparator is not inverted 0 = Output of comparator is inverted C1T0CS: Comparator TMR0 Clock Source bit(2) 1 = TMR0 clock source selected by T0CS control bit 0 = Comparator output used as TMR0 clock source C1ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off C1NREF: Comparator Negative Reference Select bit(2) 1 = C1IN- pin 0 = 0.6V VREF C1PREF: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C1IN- pin C1WU: Comparator Wake-up On Change Enable bit(2) 1 = Wake-up On Comparator Change is disabled 0 = Wake-up On Comparator Change is enabled Overrides T0CS bit for TRIS control of RB2.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence.
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REGISTER 10-2:
R-1 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CM2CON0: COMPARATOR C2 CONTROL REGISTER
R/W-1 R/W-1 C2POL R/W-1 C2PREF2 R/W-1 C2ON R/W-1 C2NREF R/W-1 C2PREF1 R/W-1 C2WU bit 0
C2OUTEN
C2OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VINC2OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C2OUT pin 0 = Output of comparator is placed in the C2OUT pin C2POL: Comparator Output Polarity bit(2) 1 = Output of comparator not inverted 0 = Output of comparator inverted C2PREF2: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C2IN- pin C2ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off C2NREF: Comparator Negative Reference Select bit(2) 1 = C2IN- pin 0 = CVREF C2PREF1: Comparator Positive Reference Select bit(2) 1 = C2IN+ pin 0 = C2PREF2 controls analog input selection C2WU: Comparator Wake-up on Change Enable bit(2) 1 = Wake-up on Comparator change is disabled 0 = Wake-up on Comparator change is enabled.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: Overrides TOCS bit for TRIS control of RC4. 2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence.
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PIC16F526
FIGURE 10-1: COMPARATORS BLOCK DIAGRAM
C1PREF C1IN+ C1IN1 0 1 0 C1NREF C1ON C1POL RB2/C1OUT C1OUTEN
+
C1OUT (Register) -
VREF (0.6V)
T0CKI
0 1 C1T0CS T0CKI Pin
Q
D
S
READ CM1CON0
C2PREF1 C2IN+ 1 0 C2PREF2 C2INC2ON 1 CVREF 0 C2NREF C2POL 1 0 +
RC4/C2OUT C2OUTEN
C2OUT (Register) -
Q C1WU
D
S CWUF C2WU
READ CM2CON0
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10.1 Comparator Operation
Note: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. A single comparator is shown in Figure 10-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of the comparator in Figure 10-2 represent the uncertainty due to input offsets and response time. See Table 14-2 for Common Mode Voltage.
10.5
Comparator Wake-up Flag
The Comparator Wake-up Flag is set whenever all of the following conditions are met: * C1WU = 0 (CM1CON0<0>) or C2WU = 0 (CM2CON0<0>) * CM1CON0 or CM2CON0 has been read to latch the last known state of the C1OUT and C2OUT bit (MOVF CM1CON0, W) * Device is in Sleep * The output of a comparator has changed state The wake-up flag may be cleared in software or by another device Reset.
FIGURE 10-2:
SINGLE COMPARATOR
VIN+ VIN-
+ -
Result
VINVIN+
10.6
Comparator Operation During Sleep
When the comparator is enabled it is active. To minimize power consumption while in Sleep mode, turn off the comparator before entering Sleep.
Result
10.7
Effects of Reset
10.2
Comparator Reference
An internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 10-2). Please see Section 11.0 "Comparator Voltage Reference Module" for internal reference specifications.
A Power-on Reset (POR) forces the CM2CON0 register to its Reset state. This forces the Comparator input pins to analog Reset mode. Device current is minimized when analog inputs are present at Reset time.
10.8
Analog Input Connection Considerations
10.3
Comparator Response Time
Response time is the minimum time after selecting a new reference voltage or input source before the comparator output is to have a valid level. If the comparator inputs are changed, a delay must be used to allow the comparator to settle to its new state. Please see Table 14-3 for comparator response time specifications.
A simplified circuit for an analog input is shown in Figure 10-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
10.4
Comparator Output
The comparator output is read through the CM1CON0 or CM2CON0 register. This bit is read-only. The comparator output may also be used externally, see Figure 10-1.
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FIGURE 10-3: ANALOG INPUT MODE
VDD RS < 10 K AIN VA CPIN 5 pF VT = 0.6V VT = 0.6V RIC
ILEAKAGE 500 nA
VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the Pin Interconnect Resistance Source Impedance Analog Voltage
TABLE 10-1:
Name STATUS CM1CON0 CM2CON0 TRIS Legend:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 Bit 6 CWUF C1OUTEN C2OUTEN -- Bit 5 PA0 C1POL C2POL Bit 4 TO C1T0CS C2PREF2 Bit 3 PD C1ON C2ON Bit 2 Z C1NREF C2NREF Bit 1 DC C1PREF C2PREF1 Bit 0 C C1WU C2WU Value on POR 0001 1xxx q111 1111 q111 1111 --11 1111 Value on All Other Resets qq0q quuu quuu uuuu quuu uuuu --11 1111
RBWUF C1OUT C2OUT --
I/O Control Register (PORTB, PORTC)
x = Unknown, u = Unchanged, - = Unimplemented, read as `0', q = Depends on condition.
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NOTES:
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11.0 COMPARATOR VOLTAGE REFERENCE MODULE
11.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 11-1) keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing the VREN bit of the VRCON register. When disabled, the reference voltage is VSS when VR<3:0> is `0000' and the VRR bit of the VRCON register is set. This allows the comparator to detect a zero-crossing and not consume the CVREF module current. The voltage reference is VDD derived and, therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage reference can be found in Section 14.0 "Electrical Characteristics".
The Comparator Voltage Reference module also allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON register (Register 11-1) controls the Voltage Reference module shown in Figure 11-1.
11.1
Configuring The Voltage Reference
The voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range. Equation 11-1 determines the output voltages:
EQUATION 11-1:
VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> x VDD/32)
REGISTER 11-1:
R/W-0 VREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 VROE R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
VREN: CVREF Enable bit 1 = CVREF is powered on 0 = CVREF is powered down, no current is drawn VROE: CVREF Output Enable bit(1) 1 = CVREF output is enabled 0 = CVREF output is disabled VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0> CVREF Value Selection bit When VRR = 1: CVREF= (VR<3:0>/24)*VDD When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD
bit 6
bit 5
bit 4 bit 3-0
Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the CVREF pin.
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FIGURE 11-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R VDD
R
R
R
R 8R VRR
VREN CVREF to Comparator 2 Input
16-1 Analog MUX
RC2/CVREF VROE
VR<3:0> VREN VR<3:0> = 0000 VRR
TABLE 11-1:
Name VRCON CM1CON0 CM2CON0 Legend:
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7 VREN Bit 6 VROE C1OUTEN C2OUTEN Bit 5 VRR C1POL C2POL Bit 4 -- C1T0CS C2PREF2 Bit 3 VR3 C1ON C2ON Bit 2 VR2 C1NREF C2NREF Bit 1 VR1 C1PREF C2PREF1 Bit 0 VR0 C1WU C2WU Value on POR 001- 1111 q111 1111 q111 1111 Value on all other Resets uuu- uuuu quuu uuuu quuu uuuu
C1OUT C2OUT
x = unknown, u = unchanged, - = unimplemented, read as `0', q = value depends on condition.
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12.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 12-1, while the various opcode fields are summarized in Table 12-1. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator which selects the number of the bit affected by the operation, while `f' represents the number of the file in which the bit is located. For literal and control operations, `k' represents an 8 or 9-bit constant or literal value. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Figure 12-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where `h' signifies a hexadecimal digit.
FIGURE 12-1:
GENERAL FORMAT FOR INSTRUCTIONS
6 5 d 4 f (FILE #) 0
Byte-oriented file register operations 11 OPCODE
d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 87 54 b (BIT #) 0 f (FILE #)
TABLE 12-1:
Field f W b k x
OPCODE FIELD DESCRIPTIONS
Description
b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 OPCODE k = 8-bit immediate value Literal and control operations - GOTO instruction 11 OPCODE k = 9-bit immediate value 9 8 k (literal) 0 8 7 k (literal) 0
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0 (store result in W) d = 1 (store result in file register `f') Default is d = 1 Label name Top-of-Stack Program Counter Watchdog Timer counter Time-out bit Power-down bit Destination, either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
d
label TOS PC WDT TO PD dest [ ( AE <> OE italics ] )
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TABLE 12-2:
Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f -- f, d f, d f, d f, d f, d f, d f, d f -- f, d f, d f, d f, d f, d
INSTRUCTION SET SUMMARY
Description Cycles 12-Bit Opcode MSb LSb Status Notes Affected
0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decrement f 1 Z 2, 4 0010 11df ffff Decrement f, Skip if 0 1(2) None 2, 4 1 0010 10df ffff Increment f Z 2, 4 1(2) 0011 11df ffff Increment f, Skip if 0 None 2, 4 1 0001 00df ffff Inclusive OR W with f Z 2, 4 1 0010 00df ffff Move f Z 2, 4 1 0000 001f ffff Move W to f None 1, 4 1 0000 0000 0000 No Operation None 1 0011 01df ffff Rotate left f through Carry C 2, 4 1 0011 00df ffff Rotate right f through Carry C 2, 4 1 0000 10df ffff C, DC, Z 1, 2, 4 Subtract W from f 1 0011 10df ffff Swap f None 2, 4 1 0001 10df ffff Exclusive OR W with f Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS 0100 bbbf ffff None 2, 4 1 Bit Clear f BCF f, b 0101 bbbf ffff None 2, 4 1 Bit Set f BSF f, b 0110 bbbf ffff None Bit Test f, Skip if Clear 1(2) BTFSC f, b 1(2) 0111 bbbf ffff None f, b Bit Test f, Skip if Set BTFSS LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL 1 k Call Subroutine 2 1001 kkkk kkkk None CLRWDT -- Clear Watchdog Timer 1 0000 0000 0100 TO, PD None GOTO k Unconditional branch 2 101k kkkk kkkk Z IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk None MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION -- Load OPTION register 1 0000 0000 0010 None RETLW k Return, place literal in W 2 1000 kkkk kkkk SLEEP -- Go into Standby mode 1 0000 0000 0011 TO, PD None 3 TRIS f Load TRIS register 1 0000 0000 0fff Z XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Note 1: The 9th bit of the program counter will be forced to a `0' by any instruction that writes to the PC except for GOTO. See Section 4.6 "Program Counter". 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of PORTB. A `1' forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).
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ADDWF Syntax: Operands: Operation: Description: Add W and f [ label ] ADDWF 0 f 31 d 01 (W) + (f) (dest) Add the contents of the W register and register `f'. If `d' is'0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d BCF Syntax: Operands: Operation: Status Affected: Description: Bit Clear f [ label ] BCF 0 f 31 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
Status Affected: C, DC, Z
ANDLW Syntax: Operands: Operation: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W).AND. (k) (W) k
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 31 0b7 1 (f) None Bit `b' in register `f' is set. f,b
Status Affected: Z The contents of the W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register.
ANDWF Syntax: Operands: Operation: Description:
AND W with f [ label ] ANDWF 0 f 31 d [0,1] (W) .AND. (f) (dest) The contents of the W register are AND'ed with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 31 0b7 skip if (f) = 0 None If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.
Status Affected: Z
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 31 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRW Syntax: Operands: Operation: Clear W [ label ] CLRW None 00h (W); 1Z Z The W register is cleared. Zero bit (Z) is set.
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k 0 k 255 (PC) + 1 Top-of-Stack; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8> None Subroutine call. First, return address (PC + 1) is PUSHed onto the stack. The eight-bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two-cycle instruction.
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD TO, PD The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 31 00h (f); 1Z Z The contents of register `f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 31 d [0,1] (f) (dest) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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DECF Syntax: Operands: Operation: Status Affected: Description: Decrement f [ label ] DECF f,d 0 f 31 d [0,1] (f) - 1 (dest) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. INCF Syntax: Operands: Operation: Status Affected: Description: Increment f [ label ] 0 f 31 d [0,1] (f) + 1 (dest) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. INCF f,d
DECFSZ Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 31 d [0,1] (f) - 1 d; None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. skip if result = 0
INCFSZ Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0 [ label ] 0 f 31 d [0,1] (f) + 1 (dest), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `0', then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. INCFSZ f,d
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 511 k PC<8:0>; STATUS<6:5> PC<10:9> None GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
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IORWF Syntax: Operands: Operation: Status Affected: Description: Inclusive OR W with f [ label ] 0 f 31 d [0,1] (W).OR. (f) (dest) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. IORWF f,d MOVWF Syntax: Operands: Operation: Status Affected: Description: Move W to f [ label ] 0 f 31 (W) (f) None Move data from the W register to register `f'. MOVWF f
MOVF Syntax: Operands: Operation: Status Affected: Description:
Move f [ label ] 0 f 31 d [0,1] (f) (dest) Z The contents of register `f' are moved to destination `d'. If `d' is `0', destination is the W register. If `d' is `1', the destination is file register `f'. `d' = 1 is useful as a test of a file register, since status flag Z is affected. MOVF f,d
NOP Syntax: Operands: Operation: Status Affected: Description:
No Operation [ label ] None No operation None No operation. NOP
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into the W register. The "don't cares" will assembled as `0's. MOVLW k 0 k 255
OPTION Syntax: Operands: Operation: Status Affected: Description:
Load OPTION Register [ label ] None (W) OPTION None The content of the W register is loaded into the OPTION register. OPTION
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RETLW Syntax: Operands: Operation: Status Affected: Description: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Status Affected: Description: SLEEP Syntax: Operands: Operation: Enter SLEEP Mode [label ] None 00h WDT; 0 WDT prescaler; 1 TO; 0 PD TO, PD, RBWUF Time-out Status bit (TO) is set. The Power-down Status bit (PD) is cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section 8.9 "Power-down Mode (Sleep)" on Sleep for more details. Subtract W from f [label ] SUBWF f,d 0 f 31 d [0,1] (f) - (W) dest) C, DC, Z Subtract (2's complement method) the W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. SLEEP
RLF Syntax: Operands: Operation: Status Affected: Description:
Rotate Left f through Carry [ label ] 0 f 31 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C
register `f'
SUBWF Syntax: Operands: Operation: Status Affected: Description:
RLF
f,d
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] 0 f 31 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C
register `f'
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 31 d [0,1] (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W register. If `d' is `1', the result is placed in register `f'.
RRF f,d
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TRIS Syntax: Operands: Operation: Status Affected: Description: Load TRIS Register [ label ] TRIS f=6 (W) TRIS register f None TRIS register `f' (f = 6 or 7) is loaded with the contents of the W register Operation: Status Affected: Description: f XORWF Syntax: Operands: Exclusive OR W with f [ label ] XORWF 0 f 31 d [0,1] (W) .XOR. (f) dest) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR literal with W [label ] XORLW k 0 k 255 (W) .XOR. k W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
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13.0 DEVELOPMENT SUPPORT
13.1
The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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13.2 MPLAB C Compilers for Various Device Families 13.5 MPLINK Object Linker/ MPLIB Object Librarian
The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
13.3
HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.
13.6
MPLAB Assembler, Linker and Librarian for Various Device Families
13.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
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PIC16F526
13.7 MPLAB SIM Software Simulator 13.9
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.
13.8
MPLAB REAL ICE In-Circuit Emulator System
13.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
2010 Microchip Technology Inc.
DS41326D-page 81
PIC16F526
13.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
13.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
13.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.
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2010 Microchip Technology Inc.
PIC16F526
14.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
Ambient temperature under bias.......................................................................................................... -40C to +125C Storage temperature ............................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................... 0 to +6.5V Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) .................................................................................................................................. 700 mW Max. current out of VSS pin ................................................................................................................................ 200 mA Max. current into VDD pin ................................................................................................................................... 150 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA Max. output current sunk by any I/O pin .............................................................................................................. 25 mA Max. output current sourced by any I/O pin ......................................................................................................... 25 mA Max. output current sourced by I/O port .............................................................................................................. 75 mA Max. output current sunk by I/O port ................................................................................................................... 75 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL)
NOTICE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2010 Microchip Technology Inc.
DS41326D-page 83
PIC16F526
FIGURE 14-1:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) 20 25 INTOSC OR EC MODE ONLY
PIC16F526 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
FIGURE 14-2:
MAXIMUM OSCILLATOR FREQUENCY TABLE
LP Oscillator Mode XT XTRC INTOSC EC HS 0 200 kHz 4 MHz Frequency 8 MHz 20 MHz
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2010 Microchip Technology Inc.
PIC16F526
14.1 DC Characteristics: PIC16F526 (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) Characteristic Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current During Prog/ Erase Supply Current(3, 4, 6) Min. 2.0 -- -- 0.05* -- -- -- -- -- -- -- -- D020 D022 D023 D022 D023 IPD IWDT ICMP Power-down Current(5) WDT Current(5) Comparator Current(5) -- -- -- -- -- -- -- -- -- -- D024 IAD* A/D Conversion Current -- -- 1.5* Vss -- 250* 175 400 250 0.75 1.4 11 38 0.1 0.35 1.0 7.0 15 60 30 75 100 175 120 200 Typ.(1) Max. 5.5 -- -- -- -- 250 700 400 1.2 2.2 22 55 1.2 2.2 3.0 16.0 26 76 75 135 120 205 150 250 Units V V V V/ms A A A A mA mA A A A A A A A A A A A A A A FOSC = 4 MHz, VDD = 2.0V FOSC = 4 MHz, VDD = 5.0V FOSC = 8 MHz, VDD = 2.0V FOSC = 8 MHz, VDD = 5.0V FOSC = 20 MHz, VDD = 5.0V FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V (per comparator) VDD = 5.0V (per comparator) VDD = 2.0V (high range) VDD = 5.0V (high range) VDD = 2.0V (reference and 1 comparator enabled) VDD = 5.0V (reference and 1 comparator enabled) 2.0V 5.0V Conditions See Figure 14-1 Device in Sleep mode See Section 8.4 "Power-on Reset (POR)" for details See Section 8.4 "Power-on Reset (POR)" for details DC Characteristics Param No. D001 D002 D003 D004 D005 D010 Sym. VDD VDR VPOR SVDD IDDP IDD
ICVREF CVREF Current(5) IFVR Internal 0.6V Fixed Voltage Reference Current(5)
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: For EXTRC mode, does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k.
2010 Microchip Technology Inc.
DS41326D-page 85
PIC16F526
14.2 DC Characteristics: PIC16F526 (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) Characteristic Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current During Prog/ Erase Supply Current(3,4,6) Min. 2.0 -- -- 0.05* -- -- -- -- -- -- -- -- D020 D022 D023 D022 D023 IPD IWDT ICMP Power-down Current(5) WDT Current(5) Comparator Current(5) -- -- -- -- -- -- -- -- -- -- D024 IAD* A/D Conversion Current -- -- 1.5* Vss -- 250* 175 400 250 0.75 1.4 11 38 0.1 0.35 1.0 7.0 15 60 30 75 100 175 120 200 Typ.(1) Max. 5.5 -- -- -- -- 250 700 400 1.2 2.2 26 110 9.0 15.0 18 22 26 76 75 135 130 220 150 250 Units V V V V/ms A A A A mA mA A A A A A A A A A A A A A A FOSC = 4 MHz, VDD = 2.0V FOSC = 4 MHz, VDD = 5.0V FOSC = 8 MHz, VDD = 2.0V FOSC = 8 MHz, VDD = 5.0V FOSC = 20 MHz, VDD = 5.0V FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V (per comparator) VDD = 5.0V (per comparator) VDD = 2.0V (high range) VDD = 5.0V (high range) VDD = 2.0V (reference and 1 comparator enabled) VDD = 5.0V (reference and 1 comparator enabled) 2.0V 5.0V Conditions See Figure 14-1 Device in Sleep mode See Section 8.4 "Power-on Reset (POR)" for details See Section 8.4 "Power-on Reset (POR)" for details DC Characteristics Param No. D001 D002 D003 D004 D005 D010 Sym. VDD VDR VPOR SVDD IDDP IDD
IcVREF CvREF Current(5) IFVR Internal 0.6V Fixed Voltage Reference Current(5)
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: For EXTRC mode, does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k.
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2010 Microchip Technology Inc.
PIC16F526
TABLE 14-1:
DC CHARACTERISTICS: PIC16F526 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified) Operating temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec. Characteristic Min. Typ. Max. Units Conditions
DC CHARACTERISTICS
Param Sym. No. VIL D030 D030A D031 D032 D033 D033 D033 VIH D040 D040A D041 D042 D042A D042A D043 D070 D060 D061 D063 VOL D080 D080A VOH D090 D090A D100 D101
D120 D120A D121
Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, T0CKI OSC1 (EXTRC mode), EC(1) OSC1 (HS mode) OSC1 (XT and LP modes) Input High Voltage I/O ports with TTL buffer 2.0 0.25VDD + 0.8V with Schmitt Trigger buffer MCLR, T0CKI OSC1 (EXTRC mode), EC(1) OSC1 (HS mode) OSC1 (XT and LP modes) 0.85VDD 0.85VDD 0.85VDD 0.7VDD 1.6 50 -- -- -- -- -- -- -- -- -- -- -- 250 -- 0.7 -- VDD VDD VDD VDD VDD VDD VDD 400 1 5 5 V V V V V V V A A A A VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C In XT, HS and LP modes when external clock is used to drive OSC1. 4.5 VDD 5.5V Otherwise For entire VDD range Vss Vss Vss Vss Vss Vss Vss -- -- -- -- -- -- -- 0.8 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD 0.3 V V V V V V V For all 4.5 VDD 5.5V Otherwise
IPUR IIL
PORTB weak pull-up current(4) Input Leakage Current(2,5) I/O ports RB3/MCLR(3) OSC1 Output Low Voltage I/O ports/CLKOUT Output High Voltage I/O ports/CLKOUT
-- -- VDD - 0.7 VDD - 0.7
-- -- -- -- -- --
1M 100K --
0.6 0.6 -- -- 15 50
-- -- 5.5
V V V V pF pF
E/W E/W V
Capacitive Loading Specs on Output Pins COSC2 OSC2 pin CIO
ED ED
-- --
100K 10K VMIN
All I/O pins and OSC2
Flash Data Memory Byte endurance Byte endurance
-40C TA +85C +85C TA +125C
VDRW VDD for read/write
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F526 be driven with external clock in RC mode. 2: Negative current is defined as coming out of the pin. 3: This spec. applies to RB3/MCLR configured as RB3 with pull-up disabled. 4: This spec. applies to all weak pull-up devices, including the weak pull-up found on RB3/MCLR. The current value listed will be the same whether or not the pin is configured as RB3 with pull-up enabled or as MCLR. 5: The leakage current on the nMCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage may be measured at different input voltages.
2010 Microchip Technology Inc.
DS41326D-page 87
PIC16F526
TABLE 14-2: COMPARATOR SPECIFICATIONS.
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C to 125C Sym. VIVRF VOS VCM CMRR
(1)*
Comparator Specifications Characteristics Internal Voltage Reference Input offset voltage Input common mode voltage* CMRR* Response Time Comparator Mode Change to Output Valid*
Min. 0.50 -- 0 55 -- --
Typ. 0.60 5.0 -- -- 150 --
Max. 0.70 10 VDD - 1.5 -- 400 10
Units V mV V db ns
s
Comments
TRT TMC2COV
* These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD - 1.5V.
TABLE 14-3:
Sym. CVRES
COMPARATOR VOLTAGE REFERENCE (VREF) SPECIFICATIONS
Characteristics Min. -- -- -- -- -- -- -- Typ. VDD/24* VDD/32 -- -- 2K* -- Max. -- -- 1/2* 1/2* -- 10* Units LSb LSb LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
Resolution Absolute Accuracy(2) Unit Resistor Value (R) Settling Time(1)
* Note 1: 2:
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. Do not use reference externally when VDD < 2.7V. Under this condition, reference should only be used with comparator Voltage Common mode observed.
DS41326D-page 88
2010 Microchip Technology Inc.
PIC16F526
TABLE 14-4: A/D CONVERTER CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min. -- -- -- -- -0.7 -- VSS -- Typ. -- -- -- -- -- guaranteed -- --
(1)
A/D Converter Specifications Param No. A01 A03 A04 A06 A07 A10 A25 A30 Sym. NR EINL Characteristic Resolution Integral Error
Max. 8 1.5 -1< EDNL 1.7 1.5 +2.2 -- VDD 10
Units bit
Conditions
LSb VDD = 5.0V LSb No missing codes to 8 bits VDD = 5.0V LSb VDD = 5.0V LSb VDD = 5.0V -- V K VSS VAIN VDD
EDNL Differential Error EOFF Offset Error EGN -- VAIN ZAIN Gain Error Monotonicity Analog Input Voltage Recommended Impedance of Analog Voltage Source
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
*
TABLE 14-5:
VDD (Volts) RB0/RB1/RB4 2.0
PULL-UP RESISTOR RANGES
Temperature (C) -40 25 85 125 -40 25 85 125 -40 25 85 125 -40 25 85 125 Min. 73K 73K 82K 86K 15K 15K 19K 23K 63K 77K 82K 86K 16K 16K 24K 26K Typ. 105K 113K 123K 132k 21K 22K 26k 29K 81K 93K 96k 100K 20k 21K 25k 27K Max. 186K 187K 190K 190K 33K 34K 35K 35K 96K 116K 116K 119K 22K 23K 28K 29K Units
5.5
RB3 2.0
5.5
2010 Microchip Technology Inc.
DS41326D-page 89
PIC16F526
14.3 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F pp 2 ck cy drt io S F H I L Fall High Invalid (high-impedance) Low P R V Z Period Rise Valid High-impedance to CLKOUT Cycle time Device Reset Timer I/O port mc osc os t0 wdt MCLR Oscillator OSC1 T0CKI Watchdog Timer Frequency T Time Lowercase subscripts (pp) and their meanings:
Uppercase letters and their meanings:
FIGURE 14-3:
LOAD CONDITIONS
Legend: pin CL VSS CL = 50 pF for all pins except OSC2 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1
DS41326D-page 90
2010 Microchip Technology Inc.
PIC16F526
FIGURE 14-4: EXTERNAL CLOCK TIMING
Q4 OSC1 1 2 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 14-6:
EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 "DC Characteristics: PIC16F526 (Industrial)" Min. DC DC DC Oscillator Frequency
(2)
AC CHARACTERISTICS
Param No. 1A
Sym. FOSC
Characteristic External CLKIN Frequency(2)
Typ.(1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4/FOSC -- -- -- -- -- --
Max. 4 20 200 4 4 20 200 -- -- -- -- 10,000 250 -- -- -- -- -- 25* 50* 15*
Units
Conditions
MHz XT Oscillator mode MHz HS/EC Oscillator mode kHz LP Oscillator mode MHz EXTRC Oscillator mode MHz XT Oscillator mode MHz HS/EC Oscillator mode kHz ns ns s ns ns ns s ns ns s ns ns ns ns XT Oscillator LP Oscillator HS/EC Oscillator XT Oscillator LP Oscillator HS/EC Oscillator LP Oscillator mode XT Oscillator mode HS/EC Oscillator mode LP Oscillator mode EXTRC Oscillator mode XT Oscillator mode HS/EC Oscillator mode LP Oscillator mode
-- 0.1 4 --
1
TOSC
External CLKIN
Period(2)
250 50 5
Oscillator Period(2)
250 250 50 5
2 3
TCY TosL, TosH TosR, TosF
Instruction Cycle Time Clock in (OSC1) Low or High Time Clock in (OSC1) Rise or Fall Time
200 50* 2* 10* -- -- --
4
* Note 1: 2:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
2010 Microchip Technology Inc.
DS41326D-page 91
PIC16F526
TABLE 14-7: CALIBRATED INTERNAL RC FREQUENCIES
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 "DC Characteristics: PIC16F526 (Industrial)" Freq. Min. Tolerance 1% 2% 5% 7.92 7.84 7.60 Typ. 8.00 8.00 8.00 Max. 8.08 8.16 8.40 Units Conditions
AC CHARACTERISTICS
Param No. F10
Sym. FOSC
Characteristic Internal Calibrated INTOSC Frequency(1)
MHz 3.5V, +25C MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.)
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
DS41326D-page 92
2010 Microchip Technology Inc.
PIC16F526
FIGURE 14-5: I/O TIMING
Q4 OSC1 Q1 Q2 Q3
I/O Pin (input) 17 I/O Pin (output) Old Value 20, 21 19 18 New Value
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 14-8:
TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) AC -40C TA +125C (extended) CHARACTERISTICS Operating Voltage VDD range is described in Section 14.1 "DC Characteristics: PIC16F526 (Industrial)" Param No. 17 18 19 20 21 Sym. TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF Characteristic OSC1 (Q1 cycle) to Port Out Valid(2), (3) OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold Port Input Valid to OSC1 (I/O in setup time) Port Output Rise Port Output Fall Time(3) Time(3) time)(2) Min. -- 50 20 -- -- Typ.(1) -- -- -- 10 10 Max. 100* -- -- 50** 58** Units ns ns ns ns ns
* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 14-3 for loading conditions.
2010 Microchip Technology Inc.
DS41326D-page 93
PIC16F526
FIGURE 14-6:
VDD MCLR 30 Internal POR 32 DRT Time-out(2) Internal Reset Watchdog Timer Reset 31 34 I/O pin(1) 34 32
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
32
Note 1: 2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. Runs in MCLR or WDT Reset only in XT, LP and HS modes.
TABLE 14-9:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 "DC Characteristics: PIC16F526 (Industrial)" Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no prescaler) Device Reset Timer Period Standard Short 9* 9* 0.5* 0.5* -- 18* 18* 1.125* 1.125* -- 30* 40* 2* 2.5* 2000* ms ms ms ms ns VDD = 5.0V (Industrial) VDD = 5.0V (Extended) VDD = 5.0V (Industrial) VDD = 5.0V (Extended) Min. 2000* 9* 9* Typ.(1) -- 18* 18* Max. -- 30* 40* Units ns ms ms Conditions VDD = 5.0V VDD = 5.0V (Industrial) VDD = 5.0V (Extended)
AC CHARACTERISTICS
Param No. 30 31 32
Sym. TMCL TWDT TDRT
34 * Note 1:
TIOZ
I/O High-impedance from MCLR low
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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FIGURE 14-7: TIMER0 CLOCK TIMINGS
T0CKI 40 42 41
TABLE 14-10: TIMER0 CLOCK REQUIREMENT
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 "DC Characteristics: PIC16F526 (Industrial)" Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N Typ.(1) Max. Units -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) Conditions
AC CHARACTERISTICS
Param Sym. No. 40 41 42 Tt0H Tt0L Tt0P
* Note 1:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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TABLE 14-11: FLASH DATA MEMORY WRITE/ERASE TIME
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 14.1 "DC Characteristics: PIC16F526 (Industrial)" Characteristic Flash Data Memory Write Cycle Time Flash Data Memory Erase Cycle Time Min. 2 2 Typ.(1) 3.5 3.5 Max. 5 5 Units ms ms Conditions
AC CHARACTERISTICS
Param No. 43 44 * Note 1:
Sym. TDW TDE
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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15.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean 3) respectively, where s is a standard deviation, over each temperature range.
FIGURE 15-1:
3.00
IDD VS. FOSC Over VDD (HS Mode)
2.50
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. 5V
2.00
IDD (mA)
1.50
Typical 5V
1.00
0.50
Max. 2V Typical 2V
0.00 5 10
Fosc (MHz)
15
20
25
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FIGURE 15-2:
800 700 600 500
TYPICAL IDD vs. FOSC OVER VDD (XT, EXTRC mode)
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
IDD (A)
400 300 200 100 0 0 1 2 3 4
5V
2V
5
FOSC (MHz)
FIGURE 15-3:
800 700 600 500
MAXIMUM IDD vs. FOSC OVER VDD (XT, EXTRC mode)
5V
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
IDD (A)
400 300
2V
200 100 0 0 1 2 3 4 5
FOSC (MHz)
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FIGURE 15-4:
120
IDD vs. VDD OVER FOSC (LP MODE)
Typical: Statistical Mean @25C Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C)
100
Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
32 kHz Maximum Extended
80
IDD (A)
60
32 kHz Maximum Industrial
40
32 kHz Typical
20
0 1 2 3 4 5 6
VDD (V)
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FIGURE 15-5:
0.45 0.40 0.35 0.30 IPD (A) 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 15-6:
18.0 16.0 14.0
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. 125C
12.0 IPD (A) 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C
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FIGURE 15-7:
9 8 7 6 IPD (A) 5 4 3 2 1 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
TYPICAL WDT IPD vs. VDD
FIGURE 15-8:
25.0
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
20.0
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. 125C
IPD (A)
15.0
10.0
5.0
Max. 85C
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 15-9: COMPARATOR IPD vs. VDD (COMPARATOR ENABLED)
80
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Maximum
60 IPD (A)
Typical
40
20
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 15-10:
50 45 40
WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)
Max. 125C
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Max. 85C 35 30 Time (ms) Typical. 25C 25 20 Min. -40C 15 10 5 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 15-11: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40xC TO 125xC)
0.8 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
0.7
Max. 125C
0.6 Max. 85C
0.5 VOL (V)
0.4 Typical 25C
0.3
0.2 Min. -40C 0.1
0.0 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
FIGURE 15-12:
0.45 0.40 0.35
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
Typical: Statistical Mean @25C Typical: Statistical Mean Temp) + Maximum: Mean (Worst-Case @25xC 3 Maximum: Meas + 3 to 125xC) (-40xC (-40C to 125C)
Max. 125C Max. 85C
0.30 0.25 Typ. 25C 0.20 0.15 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
VOL (V)
Min. -40C
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FIGURE 15-13:
3.5
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.0
Max. -40C Typ. 25C
2.5
Min. 125C 2.0 VOH (V)
1.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
1.0
0.5
0.0 0.0 -0.5 -1.0 -1.5 -2.0 IOH (mA) -2.5 -3.0 -3.5 -4.0
FIGURE 15-14:
5.5
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) ( , )
5.0 Max. -40C
Typ. 25C 4.5 VOH (V) Min. 125C
4.0
3.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 IOH (mA) -3.0 -3.5 -4.0 -4.5 -5.0
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FIGURE 15-15:
1.7 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. -40C
TTL INPUT THRESHOLD VIN vs. VDD
(TTL Input, -40xC TO 125xC)
1.5
1.3 VIN (V)
Typ. 25C 1.1 Min. 125C 0.9
0.7
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 15-16:
4.0
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
(ST Input, -40xC TO 125xC)
VIH Max. 125C 3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
VIH Min. -40C
3.0
VIN (V)
2.5
2.0 VIL Max. -40C 1.5 VIL Min. 125C
1.0
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 15-17:
45 40 35 30 DRT (ms) 25 20 15 10 5 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C Typical. 25C Min. -40C Max. 125C
DEVICE RESET TIMER (HS, XT AND LP) vs. VDD
Maximum (Sleep Mode all Peripherals Disabled)
Note:
See Table 14-9 if another clock mode is selected.
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16.0
16.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (3.90 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4 mm) XXXXXXXX YYWW NNN 16-Lead QFN Example PIC16F526 -I/PG e3 0215 0410017 Example PIC16F526-E /SLG0125 0431017 Example 16F526-I 0431 017 Example
XXX YYWW NNN
TABLE 16-1: 16-LEAD 3X3 QFN (MG) TOP MARKING
Marking MG1 MG2
MG1 0431 017
Part Number PIC16F526 - I/MG PIC16F526 - E/MG
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PIC(R) device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS41326D-page 112
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS41326D-page 114
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APPENDIX A: REVISION HISTORY
Revision A (August 2007) Original release of this document. Revision B (December 2008) Added DC and AC Characteristics graphs; Updated Electrical Characteristics section; added I/O diagrams; updated the Flash Data Memory Control Section; made various changes to the Special Features of the CPU Section and made general edits. Miscellaneous updates. Revision C (July 2009) Removed "Preliminary" status; Revised Table 6-3: I/O Pins; Revised Table 8-3: Reset Conditions; Revised Table 14-4: A/D Converter Char. Revision D (March 2010) Added Package Drawings and Package Marking Information for the 16-Lead Package Quad Flat, No Lead Package (MG) - 3x3x0.9 mm Body (QFN); Updated the Product Identification System section.
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NOTES:
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THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F526 Questions: 1. What are the best features of this document? Y N Literature Number: DS41326D FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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INDEX
A
A/D Specifications.............................................................. 89 ALU ..................................................................................... 11 Assembler MPASM Assembler..................................................... 80 Program Memory (PIC16F526) .................................. 15 Microchip Internet Web Site.............................................. 115 MPLAB ASM30 Assembler, Linker, Librarian ..................... 80 MPLAB Integrated Development Environment Software.... 79 MPLAB PM3 Device Programmer ...................................... 82 MPLAB REAL ICE In-Circuit Emulator System .................. 81 MPLINK Object Linker/MPLIB Object Librarian .................. 80
B
Block Diagram Comparator for the PIC16F526................................... 65 On-Chip Reset Circuit ................................................. 51 Timer0......................................................................... 37 TMR0/WDT Prescaler................................................. 41 Watchdog Timer.......................................................... 54 Brown-Out Protection Circuit .............................................. 55
O
Option Register................................................................... 19 OSC selection..................................................................... 43 OSCCAL Register............................................................... 20 Oscillator Configurations..................................................... 45 Oscillator Types HS............................................................................... 45 LP ............................................................................... 45 RC .............................................................................. 45 XT ............................................................................... 45
C
C Compilers MPLAB C18 ................................................................ 80 Carry ................................................................................... 11 Clock Divisors ..................................................................... 59 Clocking Scheme ................................................................ 14 Code Protection ............................................................ 43, 57 CONFIG1 Register.............................................................. 44 Configuration Bits................................................................ 43 Customer Change Notification Service ............................. 115 Customer Notification Service........................................... 115 Customer Support ............................................................. 115
P
PIC16F526 Device Varieties................................................. 9 POR Device Reset Timer (DRT) ................................... 43, 53 PD............................................................................... 55 Power-on Reset (POR)............................................... 43 TO............................................................................... 55 PORTB ............................................................................... 27 PORTC ............................................................................... 27 Power-down Mode.............................................................. 56 Prescaler ............................................................................ 40 Program Counter ................................................................ 21
D
Data Memory (SRAM and FSRs) Register File Map.................................................. 16, 17 DC and AC Characteristics ................................................. 97 Graphs and Tables ..................................................... 97 Development Support ......................................................... 79 Digit Carry ........................................................................... 11
Q
Q cycles .............................................................................. 14
R
RC Oscillator....................................................................... 46 Reader Response............................................................. 116 Read-Modify-Write.............................................................. 36 Registers CONFIG1 (Configuration Word Register 1)................ 44 Special Function ......................................................... 16 Reset .................................................................................. 43
E
Errata .................................................................................... 5
F
Flash Data Memory Control ................................................ 23 FSR ..................................................................................... 22 Fuses. See Configuration Bits
S
Sleep ............................................................................ 43, 56 Software Simulator (MPLAB SIM) ...................................... 81 Special ................................................................................ 17 Special Features of the CPU .............................................. 43 Special Function Registers ........................................... 16, 17 Stack................................................................................... 21 STATUS register................................................................. 55 Status Register ............................................................. 11, 18
I
I/O Interfacing ..................................................................... 29 I/O Ports .............................................................................. 27 I/O Programming Considerations........................................ 36 ID Locations .................................................................. 43, 57 INDF.................................................................................... 22 Indirect Data Addressing..................................................... 22 Instruction Cycle ................................................................. 14 Instruction Flow/Pipelining .................................................. 14 Instruction Set Summary..................................................... 72 Internet Address................................................................ 115
T
Timer0 Timer0 ........................................................................ 37 Timer0 (TMR0) Module .............................................. 37 TMR0 with External Clock .......................................... 39 Timing Diagrams and Specifications .................................. 91 Timing Parameter Symbology and Load Conditions .......... 90 TRIS Register ..................................................................... 27
L
Loading of PC ..................................................................... 21
M
Memory Organization.......................................................... 15 Memory Map ............................................................... 15 PIC16F526.................................................................. 15
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W
Wake-up from Sleep ........................................................... 56 Watchdog Timer (WDT) ................................................ 43, 53 Period.......................................................................... 53 Programming Considerations ..................................... 53 WWW Address.................................................................. 115 WWW, On-Line Support........................................................ 5
Z
Zero bit ................................................................................ 11
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC16F526 PIC16F526T(1) c) d) PIC16F526-E/P 301 = Extended Temp., PDIP package, QTP pattern #301 PIC16F526-I/SL = Industrial Temp., SOIC package PIC16F526T-E/P = Extended Temp., PDIP package, Tape and Reel PIC16F526T-I/MG = Industrial Temp., QFN Package, Tape and Reel
Temperature Range: Package:
I E P SL ST MG
= =
-40C to +85C (Industrial) -40C to +125C (Extended) = = = = Plastic (PDIP)(2) 14L Small Outline, 3.90 mm (SOIC)(2) Thin Shrink Small Outline (TSSOP)(2) 16-Lead 3x3 (QFN)(2) Note 1: T = in tape and reel SOIC, TSSOP and QFN packages only Pb-free.
Pattern:
Special Requirements
2:
2010 Microchip Technology Inc.
DS41326D-page 121
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/05/10
DS41326D-page 122
2010 Microchip Technology Inc.

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